AT26DF161-SU Atmel, AT26DF161-SU Datasheet - Page 22

IC FLASH 16MBIT 66MHZ 8SOIC

AT26DF161-SU

Manufacturer Part Number
AT26DF161-SU
Description
IC FLASH 16MBIT 66MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT26DF161-SU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
16M (8192 pages x 256 bytes)
Speed
66MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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22
AT26DF161
Unprotect should be performed, and two additional don’t care bits (see
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be
reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global
Protect/Unprotect” section on
The complete one byte of data must be clocked into the device before the CS pin is deasserted;
otherwise, the device will abort the operation, the state of the SPRL bit will not change, no
potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register
will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Table 10-2.
Figure 10-2. Write Status Register
SPRL
Bit 7
Write Status Register Format
SCK
SO
CS
Bit 6
SI
X
Bit 5
page 14
HIGH-IMPEDANCE
MSB
0
0
0
1
0
2
OPCODE
Global Protect/Unprotect
for more details.
0
3
Bit 4
0
4
0
5
0
6
1
7
MSB
D
8
Bit 3
STATUS REGISTER IN
X
9
D
10 11
D
D
12
Bit 2
D
13
X
14 15
X
Table
Bit 1
X
10-2). Any addi-
3599H–DFLASH–8/09
Bit 0
X

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