AT49SV322DT-80TU Atmel, AT49SV322DT-80TU Datasheet - Page 4

• Manufacturer Part Number: AT49SV322DT-80TU
• Description: IC FLASH 32MBIT 80NS 48TSOP
• Manufacturer: Atmel

Specifications of AT49SV322DT-80TU

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (2M x 16)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
4.4
4.4.1
4.4.2
4.5
4
Reset
Erase
Word Programming
AT49SV322D(T)
Chip Erase
Sector Erase
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts
the present device operation and puts the outputs of the device in a high impedance state.
When a high level is reasserted on the RESET pin, the device returns to the read or standby
mode, depending upon the state of the control inputs.
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The entire device can be erased by using the Chip Erase command or individual
sectors can be erased by using the Sector Erase command.
The entire device can be erased at one time by using the six-word chip erase software code.
After the chip erase has been initiated, the device will internally time the erase operation so
that no external clocks are required. The maximum time to erase the chip is t
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that
can be individually erased. The Sector Erase command is a six-bus cycle operation. The sec-
tor address is latched on the falling WE edge of the sixth cycle while the 30H data input
command is latched on the rising edge of WE. The sector erase starts after the rising edge of
WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to
completion. The maximum time to erase a sector is t
down feature is not enabled, the sector will erase (from the same Sector Erase command). An
attempt to erase a sector that has been protected will result in the operation terminating
immediately.
Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the internal device command register and is a four-bus
cycle operation. The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
SEC
. When the sector programming lock-
EC
.
3623A–FLASH–7/06
BP
cycle