MT48LC8M8A2TG-7E L:G TR Micron Technology Inc, MT48LC8M8A2TG-7E L:G TR Datasheet - Page 34

IC SDRAM 64MBIT 133MHZ 54TSOP

MT48LC8M8A2TG-7E L:G TR

Manufacturer Part Number
MT48LC8M8A2TG-7E L:G TR
Description
IC SDRAM 64MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48LC8M8A2TG-7E L:G TR

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (8M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power-Down
Figure 24:
Figure 25:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Terminating a WRITE Burst
PRECHARGE Command
Note:
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (
performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
A0–A9
BA0,1
RAS#
CAS#
ADDRESS
WE#
CKE
CLK
A10
CS#
DQMs are LOW.
CLK
TRANSITIONING DATA
DQ
HIGH
VALID ADDRESS
BANK,
WRITE
COL n
D
T0
n
IN
TERMINATE
Bank Selected
BURST
T1
All Banks
ADDRESS
BANK
DON’T CARE
COMMAND
(ADDRESS)
(DATA)
NEXT
T2
34
DON’T CARE
t
REF or
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF
t
CKS). See Figure 26 on page 35.
AT
) since no refresh operations are
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands

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