CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet
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CY7C1354A-166BGC
Specifications of CY7C1354A-166BGC
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CY7C1354A-166BGC Summary of contents
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... Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc, and BWd), and Read-Write Control (R/W). BWc and BWd ap- ply to CY7C1354A/GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data oc- curs, either read or write ...
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... The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. PRELIMINARY [1] Address Control Input Registers Control Logic Output Registers Output Buffers [1] Address Control Input Registers Control Logic Output Registers Output Buffers 2 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Sel Mux DQa-DQd Sel Mux DQa, DQb ...
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... DQb DQa 18 63 DQa DQb CCQ 61 CCQ DQa DQb 22 59 DQa DQb 23 58 DQa DPb 24 57 DQa CCQ 54 CCQ DQa DQa DQa CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 CY7C1356A GVT71512ZC18 65 (512K x 18 CCQ DQa DQa DQa CCQ DQa DQa DQa DQa V CCQ V SS DQa DQa ...
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... Pin Configurations (continued) CY7C1354A/GVT71256ZC36 (256K x 36 BGA CCQ DQc E DQc F V CCQ G DQc H DQc J V CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CY7C1356A/GVT71512ZC18 (512K x 18 BGA CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb CCQ PRELIMINARY 119-Ball Bump BGA ...
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... CLK Input- Clock: This is the clock input to CY7C1354A/GVT71256ZC36. Synchronous Except for OE, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK. ...
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... R/W is sampled HIGH. The appropriate byte(s) of data are written into the device two cycles later. BWa con- trols DQa pins; BWb controls DQb pins. BWx can all be tied LOW if always doing write to the entire 18-bit word. 6 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description . GND ...
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... Output IEEE 1149.1 test output. LVTTL-level output. If Serial Bound- ary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect). V Supply Power Supply: +3.3V –5% and +5 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description are used 2 sampled LOW, along with ADV/ used with CE 2 has inverted polarity but oth- 2 ...
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... Linear Burst Address Table (MODE = V Fourth First Address Address [5] (internal) (external) A...A A... A...A A... A...A A... A...A A... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description or to GND. CC [4] BWb BWc BWd Second Third Fourth Address Address Address (internal) (internal) (internal) A...A A...A A... A...A A...A A... ...
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... Previous Address Cycle Used R/W ADV/ Deselect External H L Read Next External H L Read Next External L L Write Next External L L Write Next being HIGH. CE equals L means CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 n+24 n+25 n+26 n+ CKE BWx OE (2 cycles later High High High High-Z ...
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... The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number. 10 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ) ...
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... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. 11 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 plus The ...
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... IDLE Note: 21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. PRELIMINARY 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram 12 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [21 ...
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... OLC [23, 25 100 A OHC [23 8.0 mA OLT [23 8.0 mA OHT (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Selection Circuitry [22] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –30 30 –5.0 5 ...
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... THMX t Capture Hold CH Notes: 26. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register 27. Test conditions are specified using the load in TAP AC test conditions. PRELIMINARY [26, 27] Over the Operating Range Description 14 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Min. Max ...
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... TAP Timing and Test Conditions 1.5V 50 TDO GND ( TEST CLOCK (TCK) TEST MODE SELECT (TMS) TEST DATA IN (TDI) TEST DATA OUT (TDO) PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ALL INPUT PULSES 3.0V 1.5V 1 ...
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... Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Places the bypass register between TDI and TDO. This instruction does not affect device operations. 16 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description Reserved for revision number. Defines depth of 256K or 512K words. ...
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... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump ID CE2 92 6B BWa 93 5L BWb 94 5G BWc 95 3G BWd 96 3L CE2 100 2A DQc 1 2D DQc 2 1E DQc 3 2F DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 2E DQc 12 2G DQc DQd 18 2K DQd 19 1L DQd 22 2M ...
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... R/W 88 PRELIMINARY Boundary Scan Order (512K x 18) Bit# Bump CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump ID CLK 89 4K CE2 92 6B BWa 93 5L BWb 94 3G CE2 100 2A DQb 8 1D DQb 9 2E DQb 12 2G DQb DQb 18 2K DQb 19 1L DQb 22 2M DQb 23 1N DQb ...
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... Device deselected; all inputs < > all inputs static Max.; CLK frequency = 0 CC Device deselected; all inputs < > MAX CLK cycle time > t Min means no input lines are changing. CYC 19 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Ambient [11] Temperature +70 C 3.3V Min. Max. 2.0 V +0.3 CC 2.0 4.6 –0.5 0 ...
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... AC Test Loads and Waveforms for 2.5V I 1.25V t (a) PRELIMINARY Description Test Conditions MHz 3.3V CC Test Conditions 317 3. 351 (b) 2. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Typ. Max. Unit 6.5 pF Symbol TQFP Typ. Units 25 C C/W JC ALL INPUT PULSES 90% 90% 10% 10% 1.0 ns (c) ALL INPUT PULSES 90% 90% 10% 10% 1 ...
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... KQHZ KQLZ OEHZ 21 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 -7.5/ -10/ 133 MHz 100 MHz Max. Min. Max. Min. Max. 7.5 10 2.6 3.5 2.6 3.5 3.6 4.2 5.0 1.0 1 ...
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... BURST PIPELINE READ Pipeline Read . Q(A ) represents the first output from the external address etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined 2 is HIGH CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 (Burst Wraps around to initial state) Q(A +2) Q(A +3) Q ...
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... Burst Pipeline Write Pipeline Write ) represents the first input to the external address etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the 2 23 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 BW (Burst Wraps around to initial state) D(A +2) D(A ...
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... KQ DATA Out (Q) Read DATA In (D) Note: 46. Q(A ) represents the first output from the external address A 1 PRELIMINARY BW KQHZ KQLZ KQX Q Read D Write Write . D(A ) represents the input data to the SRAM corresponding to address CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Q(A ) Q(A 6 Read D ...
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... CKE when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM will retain their previous state. PRELIMINARY KQHZ Q KQLZ KQX 25 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ...
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... This allows for any pending data transfers (reads or writes completed. PRELIMINARY KQHZ Q KQX D(A ) represents the input data to the SRAM corresponding to address sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 OEHZ Q D etc. 3 ...
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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1354A-200AC/ GVT71256ZC36-5 CY7C1354A-200BGC/ GVT71256ZC36B-5 166 CY7C1354A-166AC/ GVT71256ZC36-6 CY7C1354A-166BGC/ GVT71256ZC36B-6 133 CY7C1354A-133AC/ GVT71256ZC36-7.5 CY7C1354A-133BGC/ GVT71256ZC36B-7.5 100 CY7C1354A-100AC/ GVT71256ZC36-10 CY7C1354A-100BGC/ GVT71256ZC36B-10 200 CY7C1356A-200AC/ GVT71512ZC18-5 CY7C1356A-200BGC/ GVT71512ZC18B-5 166 CY7C1356A-166AC/ GVT71512ZC18-6 CY7C1356A-166BGC/ GVT71512ZC18B-6 133 CY7C1356A-133AC/ GVT71512ZC18-7.5 CY7C1356A-133BGC/ GVT71512ZC18B-7.5 ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 PRELIMINARY 28 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 51-85050-A ...
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... Package Diagrams (continued) Revision History Document Title: CY7C1354A/CY7C1356A Document Number: 38-00992 REV. ECN NO. ISSUE DATE ** 3000 4/21/00 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...