CY7C057V-15AC Cypress Semiconductor Corp, CY7C057V-15AC Datasheet - Page 19

• Manufacturer Part Number: CY7C057V-15AC
• Description: IC SRAM 1.152MBIT 15NS 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C057V-15AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1.152M (32K x 36)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1174

Right Port Configuration
Right Port Operation
Left Port Operation
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t
be obtained by one side or the other, but there is no guarantee
which side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
Document #: 38-06055 Rev. **
Notes:
47. BM and SIZE must be configured one clock cycle before operation is guaranteed.
48. In x36 mode WA and BA pins are “Don’t Care.”
49. In x18 mode BA pin is a “Don’t Care.”
50. DQ represents data output of the chip.
Configuration
x36
x18
x18
x9
x9
x9
x9
BM
0
0
1
1
SPS
of each other, the semaphore will definitely
Control Pin
B0
B1
B2
B3
[47, 48, 49]
WA
X
0
1
0
0
1
1
SIZE
0
1
0
1
BA
X
X
X
0
1
0
1
x36 (CE Active SEM Mode)
semaphore within t
be obtained by one side or the other, but there is no guarantee
which side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t
be obtained by one side or the other, but there is no guarantee
which side will control the semaphore.
Data Accessed
x36 (Standard)
Configuration
DQ
DQ
DQ
x18
DQ
DQ
DQ
DQ
x9
18–35
18–26
27–35
0–35
0–17
9–17
0–8
I/O
I/O
I/O
SPS
SPS
I/O
18–26
27–35
9–17
[50]
0–8
of each other, the semaphore will definitely
of each other, the semaphore will definitely
Effect
Byte Control
Byte Control
Byte Control
Byte Control
I/O Pins Used
I/O Pins Used
I/O
I/O
I/O
CY7C056V
CY7C057V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0–35
0–35
0–17
0–8
0–35
0–17
0–17
0–8
0–8
0–8
0–8
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