M27C256B-12C1 STMicroelectronics, M27C256B-12C1 Datasheet - Page 8

• Manufacturer Part Number: M27C256B-12C1
• Description: IC OTP 256KBIT 120NS 32PLCC
• Manufacturer: STMicroelectronics

Specifications of M27C256B-12C1

• Format - Memory: EPROMs
• Memory Type: OTP EPROM
• Memory Size: 256K (32K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1644-5

Device operation
2
2.1
2.2
2.3
8/24
Device operation
The operating modes of the M27C256B are listed in the Operating Modes. A single power
supply is required in the read mode. All inputs are TTL levels except for V
for Electronic Signature.
Read mode
The M27C256B has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
available at the output after delay of t
been low and the addresses have been stable for at least t
Standby mode
The M27C256B has a standby mode which reduces the supply current from 30mA to
100µA. The M27C256B is placed in the standby mode by applying a CMOS high signal to
the E input. When in the standby mode, the outputs are in a high impedance state,
independent of the G input.
Two-line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is desired from a particular memory device.
the lowest possible memory power dissipation,
complete assurance that output bus contention will not occur.
AVQV
) is equal to the delay from E to output (t
GLQV
from the falling edge of G, assuming that E has
AVQV
-t
GLQV
.
ELQV
PP
and 12V on A9
). Data is
M27C256B