M29F400BT70N6 NUMONYX, M29F400BT70N6 Datasheet
M29F400BT70N6
Specifications of M29F400BT70N6
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M29F400BT70N6 Summary of contents
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... Defectivity below 1 ppm/year March 2007 4 Mbit (512Kb x8 or 256Kb x16, Boot Block) single supply Flash memory Electronic signature – Manufacturer Code: 0020h – Top Device Code M29F400BT: 00D5h – Bottom Device Code M29F400BB: 00D6h ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M29F400BT, M29F400BB 4.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M29F400BT, M29F400BB List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description 1 Description The M29F400B Mbit (512 256 Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29F400B is fully backward compatible with the M29F400. ...
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M29F400BT, M29F400BB Figure 1. Logic diagram Table 1. Signal names A0-A17 DQ0-DQ7 DQ8-DQ14 DQ15A– BYTE A0-A17 W M29F400BT E M29F400BB Address Inputs ...
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Description Figure 2. TSOP connections 8/40 A15 1 48 A14 A13 A12 A11 A10 M29F400BT M29F400BB A17 ...
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M29F400BT, M29F400BB Figure 3. SO connections A17 M29F400BT ...
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... Logic Diagram, and connected to this device. 2.1 Address inputs (A0-A17) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. 2.2 ...
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... PHPHH 2.9 Ready/Busy output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance ...
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... This prevents Bus Write operations from accidentally damaging the data LKO during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the V Ground pin to decouple the current surges from the power supply ...
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... Enable are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V ...
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... They require V applied to some pins. 3.6.1 Electronic Signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in and Table 3 ...
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M29F400BT, M29F400BB Table 3. Bus operations, BYTE = V Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code (1) IH Address Inputs A0-A17 ...
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... Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10 period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. 4.2 ...
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... Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory ...
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... When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 4.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks ...
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... Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. ...
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... Program, Unlock Bypass Program, Chip Erase, Block Erase After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until Timeout Bit is set. ...
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... After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. 4.15 Unlock Bypass Reset After the Unlock Bypass Reset command read the memory as normal until another command is issued. 4.16 Erase Suspend After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal ...
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... DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’ ...
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... Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at ’ ...
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Status Register Table 6. Status Register bits Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout Block Erase Erase Suspend Erase Error 1. Unspecified data bits should be ignored. Figure 4. Data polling flowchart 24/40 ...
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M29F400BT, M29F400BB Figure 5. Data toggle flowchart START READ DQ5 & DQ6 READ DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370B Status Register 25/40 ...
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Maximum rating 6 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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... Program and erase times and endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 8. Exact erase times may change depending on the memory array condition. Table 8. Program/ Erase times endurance cycles Parameter Chip Erase (All bits in the memory set to ‘0’) ...
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DC and AC parameters 8 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests ...
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M29F400BT, M29F400BB Figure 7. AC testing load circuit Table 10. Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT ° MHz A 2. Sampled only, not 100% tested. 1.3V 1N914 3.3k DEVICE ...
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DC and AC parameters Table 11. DC characteristics Symbol I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) CC1 Supply Current (Standby) I CC2 TTL Supply Current (Standby) I CC3 CMOS Supply Current (3) I ...
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M29F400BT, M29F400BB Figure 8. Read mode AC waveforms A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH Table 12. Read AC characteristics Symbol Alt Address Valid to Next Address t t AVAV RC Valid t t Address Valid to Output Valid ...
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DC and AC parameters Figure 9. Write AC waveforms, Write Enable controlled A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 Table 13. Write AC characteristics, Write Enable controlled Symbol Alt t t AVAV ELWL CS ...
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M29F400BT, M29F400BB Figure 10. Write AC waveforms, Chip Enable controlled A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 Table 14. Write AC characteristics, Chip Enable controlled Symbol Alt t t AVAV WLEL ...
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DC and AC parameters Figure 11. Reset/Block Temporary Unprotect AC waveforms Table 15. Reset/Block Temporary Unprotect AC characteristics Symbol Alt (2) t PHWL t t PHEL RH (2) t PHGL (2) t RHWL (2) t ...
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M29F400BT, M29F400BB 9 Package mechanical Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, package outline DIE 1. Drawing is not to scale. Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, ...
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Package mechanical Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package outline 44 1 SO-F 1. Drawing is not to scale. Table 17. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package ...
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... Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you ...
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Block address tables Appendix A Block address tables Table 19. Top boot block addresses, M29F400BT Size # (Kbytes ...
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M29F400BT, M29F400BB Revision history Table 21. Document revision history Date July 1999 09/21/99 10/04/99 07/28/00 19-Sep-2005 20-Jul-2006 12-Dec-2006 22-Mar-2007 Revision First Issue Chip Erase Max. specification added Block Erase Max. specification added Program Max. specification added Chip Program Max. specification ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...