M29W320DB70N6 NUMONYX, M29W320DB70N6 Datasheet - Page 10

• Manufacturer Part Number: M29W320DB70N6
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W320DB70N6

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1714

M29W320DT, M29W320DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, V
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
Protect pin provides two functions. The V
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Unlock Bypass Program operations. The
Write Protect function provides a hardware meth-
od of protecting the 16 Kbyte Boot Block. The
V
unconnected.
When V
protects the 16 Kbyte Boot Block; Program and
Erase operations in this block are ignored while
V
10/44
IH
PP/
PP
PP
. When BYTE is Low, V
/Write Protect pin must not be left floating or
/Write Protect is Low.
Write Protect (V
IH
PP
, all other pins are ignored.
/Write Protect is Low, V
IL
, this pin behaves as an address
PP
/WP). The
IH
, this pin behaves as a
IL
, these pins are not
IL
, the memory
V
PP
PP
/Write
func-
When V
reverts to the previous protection status of the 16
Kbyte boot block. Program and Erase operations
can now modify the data in the 16 Kbyte Boot
Block unless the block is protected using Block
Protection.
When V
ory automatically enters the Unlock Bypass mode.
When V
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t
Never raise V
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
A 0.1µF capacitor should be connected between
the V
to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Unlock Bypass
Program, I
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
outermost boot block will remain protect even if RP
is at V
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
goes High, V
Read and Bus Write operations after t
t
Output section, Table 15 and Figure 14, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
PLPX
RHEL
PHPHH
IH
to V
PP
. After Reset/Block Temporary Unprotect
, whichever occurs last. See the Ready/Busy
VHVPP
ID
.
/Write Protect pin and the V
PP
PP
.
PP
PP
/Write Protect is raised to V
/Write Protect is High, V
/Write Protect returns to V
PP
, see Figure 15.
and from V
.
IH
PP
PP
, the memory will be ready for Bus
/WP is at V
/Write Protect to V
ID
will temporarily unprotect the
IH
OL
to V
PP
. Ready/Busy is high-im-
to V
ID
IL
must be slower than
, then the 16 KByte
IH
must be slower
IH
SS
IL
, the memory
IH
PP
, for at least
PP
Ground pin
or V
the mem-
from any
PHEL
PP
IL
from
nor-
or