PSD834F2-90M STMicroelectronics, PSD834F2-90M Datasheet - Page 54
![IC FLASH 2MBIT 90NS 52QFP](/photos/7/25/72513/497-52-pqfp_series_sml.jpg)
PSD834F2-90M
Manufacturer Part Number
PSD834F2-90M
Description
IC FLASH 2MBIT 90NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2VA-20JI.pdf
(109 pages)
Specifications of PSD834F2-90M
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2008
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD834F2-90M
Manufacturer:
ROCKCHIP
Quantity:
1 302
Company:
Part Number:
PSD834F2-90M
Manufacturer:
ST
Quantity:
490
Company:
Part Number:
PSD834F2-90M
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
PSD834F2-90M
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
PSD834F2-90MI
Manufacturer:
ACTIVE
Quantity:
12 000
Company:
Part Number:
PSD834F2-90MI
Manufacturer:
WSI
Quantity:
10
Company:
Part Number:
PSD834F2-90MI
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD813F2V, PSD854F2V
Table 20. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
Table 21. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
54/109
MCU I/O
PLD I/O
Data Port (Port A)
Address Out
(Port A,B)
Address In
(Port A,B,C,D)
Peripheral I/O
(Port A)
JTAG ISP (Note
8051XA (8-Bit)
80C251
(Page Mode)
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed Bus
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
3. Any of these three methods enables the JTAG pins on Port C.
term (.oe) from the CPLD AND Array.
Mode
MCU
3
)
Declare pins only
Logic equations
N/A
Declare pins only
Logic for equation
Input Macrocells
Logic equations
(PSEL0 & 1)
JTAGSEL
N/A
N/A
Address a3-a0
N/A
Port A (PA3-PA0)
Defined in
1
PSDabel
N/A
N/A
Specify bus type
N/A
N/A
N/A
JTAG
Configuration
Doc ID 10552 Rev 3
Defined in PSD
Configuration
1
Address a7-a4
N/A
Address a7-a4
N/A
Port A (PA7-PA4)
N/A
0
N/A
1
N/A
N/A
N/A
Register
Control
Setting
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (PB3-PB0)
1 = output,
0 = input
(Note
(Note
N/A
1 (Note
N/A
N/A
N/A
Direction
Register
Setting
2
2
)
)
2
)
N/A
N/A
N/A
N/A
N/A
PIO bit = 1 N/A
N/A
Register
Setting
VM
N/A
Address a15-a12
Address a7-a4
Address a7-a4
Port B (PB7-PB4)
N/A
N/A
N/A
N/A
N/A
JTAG_Enable
JTAG Enable