CY7C1354B-166BGC Cypress Semiconductor Corp, CY7C1354B-166BGC Datasheet - Page 8

• Manufacturer Part Number: CY7C1354B-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354B-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05114 Rev. *C
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH
(DQ
CY7C1356B) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ
DQP
CY7C1356B) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct BW
(BW
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
ZZ Mode Electrical Characteristics
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d
a,b,c,d
a,b,c,d
Parameter
before
/DQP
for CY7C1354B and BW
for
a,b,c,d
presenting
CY7C1354B
for CY7C1354B and DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
, CE
data
2
, and CE
Description
and
a,b
to
for CY7C1356B) inputs
3
the
and DQP
DQ
) and WE inputs are
a,b
DQ
a,b
/DQP
/DQP
(DQ
and
a,b
a,b
a,b,c,d
DQP
for
for
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
/
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
DD
DD
Address
Address
Test Conditions
− 0.2V
− 0.2V
A1,A0
A1,A0
First
First
00
01
10
00
01
10
11
11
ZZREC
Address
Address
Second
Second
A1,A0
A1,A0
1
01
10
00
11
, CE
01
00
11
10
after the ZZ input returns LOW.
2
, and CE
DD
)
2t
Address
Address
Min.
A1,A0
CYC
A1,A0
Third
3,
0
Third
10
00
01
11
10
00
01
11
must remain inactive for
CY7C1356B
CY7C1354B
2t
2t
Max
35
CYC
CYC
Page 8 of 29
Address
Address
Fourth
Fourth
A1,A0
A1,A0
10
01
00
11
00
01
10
11
Unit
mA
ns
ns
ns
ns