CY7C136-55JXIT Cypress Semiconductor Corp, CY7C136-55JXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C136-55JXIT
• Description: IC SRAM 16KBIT 55NS 52PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C136-55JXIT

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 16K (2K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Density: 16Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 22b
• Package Type: PLCC
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 110mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 8b
• Number Of Words: 2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55)
Document #: 38-06031 Rev. *E
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Busy/Interrupt Timing
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
DDD
WDD
Parameter
[12]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
Description
[7, 10]
[7, 10]
[7, 10, 11]
[7, 10, 11]
[7]
[7]
[9]
[7]
[9]
[9]
[7]
[13]
[14]
[8]
[13]
Min
35
35
30
30
25
15
30
0
3
5
0
2
0
0
0
5
0
7C132-35
7C136-35
7C142-35
7C146-35
Note 15
Note 15
Max
35
35
20
20
20
35
20
20
20
20
20
35
CY7C136A, CY7C142, CY7C146
Min
45
45
35
35
30
20
35
0
3
5
0
2
0
0
0
5
0
7C132-45
7C136-45
7C142-45
7C146-45
Note 15
Note 15
Max
45
45
25
20
20
35
20
25
25
25
25
45
CY7C132, CY7C136
Min
55
55
40
40
30
20
35
7C136A-55
0
3
5
0
2
0
0
0
5
0
7C132-55
7C136-55
7C142-55
7C146-55
Note 15
Note 15
Max
55
55
25
25
25
35
25
30
30
30
30
45
Page 6 of 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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