CY7C1399B-15VXI Cypress Semiconductor Corp, CY7C1399B-15VXI Datasheet

IC SRAM 256KBIT 15NS 28SOJ

CY7C1399B-15VXI

Manufacturer Part Number
CY7C1399B-15VXI
Description
IC SRAM 256KBIT 15NS 28SOJ
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1399B-15VXI

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
256K (32K x 8)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document #: 38-05071 Rev. *D
Features
Functional Description
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
Selection Guide
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
• Low active power
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
— 10/12/15 ns
— 216 mW (max.)
Logic Block Diagram
CE
WE
OE
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
[1]
INPUT BUFFER
DECODER
32K x 8
COLUMN
ARRAY
L
• 3901 North First Street
1399B-10
POWER
DOWN
500
10
60
50
1399B-12
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
500
12
55
50
0
through I/O
• San Jose
256K(32K x 8) Static RAM
14
). Reading the device is accomplished by selecting
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
1399B-15
500
15
50
50
7
,
) is written into the memory location
CA 95134
Pin Configurations
GND
I/O 0
I/O
I/O
A
A
A
A
A
1399B-20
A
A
A
A
A
10
11
12
13
14
5
6
7
8
9
1
2
500
20
45
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Revised July 11, 2005
Top View
SOJ
408-943-2600
CY7C1399B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
4
3
2
1
0
3
7
6
5
4
Unit
mA
µA
µA
ns
0

Related parts for CY7C1399B-15VXI

CY7C1399B-15VXI Summary of contents

Page 1

... The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399B is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. POWER DOWN ...

Page 2

... I CC Output Disabled V = Max GND CC OUT V = Max mA, CC OUT 1/t MAX ≥ V Max ≥ V ≤ MAX , CE ≥ V Max. V – 0.3V [4] ≤ 0.3V, V – 0.3V ≥V – 0. ≤0.3V MAX CY7C1399B I GND Ambient Temperature ° ° 3.3V ±300 +70 C ° ...

Page 3

... CC IN [4] ≥ V ≤ 0.3V, – 0.3V WE≥V –0.3V or WE≤ 0.3V, CC f=f MAX Description Test Conditions T = 25° MHz 351Ω 1.73V CY7C1399B 1399B-15 1399B-20 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 +0.3V +0.3V –0.3 0.8 –0.3 0.8 – ...

Page 4

... The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t Document #: 38-05071 Rev. *D [6] Description [7] [7, 8] [7] [7, 8] [9] [7] is less than less than t HZCE LZCE HZOE = Test Loads. Transition is measured ±500 mV from steady state voltage. CY7C1399B 1399B-10 1399B-12 Min. Max. Min. Max ...

Page 5

... CDR Retention Time t Operation Recovery Time R Document #: 38-05071 Rev. *D [6] (continued) Description [7] [7, 8] [7] [7, 8] [9] [7] (Over the Operating Range - L version only) Description Conditions Com’ 2.0V > V – 0.3V > V – 0. < 0.3V IN CY7C1399B 1399B-15 1399B-20 Min. Max. Min. Max ...

Page 6

... Device is continuously selected HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05071 Rev. *D DATA RETENTION MODE > CDR OHA ACE t DOE t LZOE 50 CY7C1399B 3. DATA VALID t HZOE t HZCE IMPEDANCE DATA VALID t PD 50% HIGH ICC ISB Page ...

Page 7

... If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 38-05071 Rev. *D [9, 14, 15 PWE t SD DATA IN [9, 14, 15 DATA [10, 15 DATA t HZWE CY7C1399B VALID SCE VALID VALID IN t LZWE Page ...

Page 8

... Ordering Code 12 CY7C1399B-12VC CY7C1399B-12VXC CY7C1399B-12ZC CY7C1399B-12ZXC CY7C1399BL-12ZC CY7C1399BL-12ZXC CY7C1399B-12VXI 15 CY7C1399B-15VC CY7C1399B-15VXC CY7C1399B-15ZC CY7C1399B-15ZXC CY7C1399BL-15VC CY7C1399BL-15VXC CY7C1399BL-15ZXC CY7C1399B-15VI CY7C1399B-15VXI CY7C1399B-15ZI CY7C1399B-15ZXI 20 CY7C1399B-20ZC CY7C1399B-20ZXC Document #: 38-05071 Rev. *D Mode Deselect/Power-Down Read Write Deselect, Output Disabled Package Name Package Type V21 28-Lead Molded SOJ V21 ...

Page 9

... Cypress against all charges. 28-Lead (300-Mil) Molded SOJ V21 MIN. MAX. PIN 0.291 0.330 0.300 0.350 28 SEATING PLANE 0.120 0.140 0.004 0.025 MIN. CY7C1399B A DETAIL EXTERNAL LEAD DESIGN 0.026 0.032 0.013 0.014 0.019 0.020 OPTION 1 OPTION 2 0.007 0.013 0.262 0.272 ...

Page 10

... Document History Page Document Title: CY7C1399B 256K(32K x 8) Static RAM Document Number: 38-05071 ISSUE REV. ECN NO. DATE ** 107264 05/25/01 *A 107533 06/28/01 *B 116472 09/17/02 *C 224340 See ECN *D 386100 See ECN Document #: 38-05071 Rev. *D ORIG. OF CHANGE DESCRIPTION OF CHANGE SZV Change from Spec #: 38-01102 to 38-05071 ...

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