M24C04-WMN6P STMicroelectronics, M24C04-WMN6P Datasheet - Page 8

• Manufacturer Part Number: M24C04-WMN6P
• Description: IC EEPROM 4KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24C04-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 512 x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Capacitance, Input: 8 pF (SDA), 6 pF (Other Pins)
• Current, Input, Leakage: ±2 μA
• Current, Operating: 2 mA
• Current, Output, Leakage: ±2
• Current, Supply: 3 mA
• Data Retention: >40 yrs.
• Density: 4K
• Package Type: SO8
• Temperature, Operating: -40 to +85 °C
• Temperature, Operating, Maximum: 85 °C
• Temperature, Operating, Minimum: -40 °C
• Time, Access: 900 ns
• Time, Fall: 50 ns
• Time, Rise: 50 ns
• Voltage, Esd: 4000 V
• Voltage, Input, High: 3.5 to 6.5 V
• Voltage, Input, High Level: 0.7 V
• Voltage, Input, Low: 0.75 to 1.65 V
• Voltage, Input, Low Level: –0.45 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.5 to 5.5 V
• Memory Configuration: 512 X 8
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8562; M24C04-WMN6P

M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in
7., and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High (during the period from
8/29
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
NO ACK
DEV SEL
DEV SEL
DATA IN N
th
R/W
R/W
bit” time
ACK
ACK
Figure
NO ACK
BYTE ADDR
BYTE ADDR
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by gener-
ating a Stop condition, as shown in
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
DATA IN 2
Figure
NO ACK
6., and the location is
DATA IN 3
AI02803C
Figure
7..