M25P80-VMN3P/4 NUMONYX, M25P80-VMN3P/4 Datasheet - Page 18

• Manufacturer Part Number: M25P80-VMN3P/4
• Description: IC SRL FLASH 8MBIT 3V SO8 AUTO
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMN3P/4

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Instructions
All instructions, addresses, and data are shifted in and out of the device, most significant bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C). The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-
down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 4.
FAST_READ
Instruction
RDID
WREN
WRSR
RDSR
READ
WRDI
PP
SE
BE
DP
(1)
Instruction set
Write Enable
Write Disable
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
Read Data Bytes at Higher
Speed
Page Program
Sector Erase
Bulk Erase
Deep Power-down
Description
instruction code
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
0000 1011
1101 1000
1011 1001
1001 1111
1100 0111
One-byte
Table
4.
0Bh
D8h
C7h
B9h
06h
04h
9Fh
05h
01h
03h
02h
Address
bytes
0
0
0
0
0
3
3
3
3
0
0
Dummy
bytes
0
0
0
0
0
0
1
0
0
0
0
1 to 256
1 to 20
1 to ∞
1 to ∞
1 to ∞
bytes
Data
0
0
1
0
0
0