M25PE10-VMP6TG NUMONYX, M25PE10-VMP6TG Datasheet - Page 29

• Manufacturer Part Number: M25PE10-VMP6TG
• Description: IC FLASH 1MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE10-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE10-VMP6TGCT

M25PE20, M25PE10
6.5
Note:
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register.
The Status Register BPi and SRWD bits are available in the T9HX process only. See
Important note on page 6
Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in
user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal (see
If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the
internal cycle of the Write Status Register operation (whose duration is t
(provided that the supply voltage V
device enters the Reset mode (see also
and
Figure 12. Write Status Register (WRSR) instruction sequence
Table 26: Timings after a Reset Low
S
C
D
Q
Table
3. The Write Status Register (WRSR) instruction also allows the
for more details.
0
1
Section
High Impedance
2
Instruction
CC
3
Figure
6.4.4).
4
remains within the operating range). After that the
Table 14: Device status after a Reset Low pulse
5
pulse).
6
12.
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
W
) is first completed
AI02282D
Instructions
W
) is
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