NAND512R3A2CZA6E NUMONYX, NAND512R3A2CZA6E Datasheet - Page 27

• Manufacturer Part Number: NAND512R3A2CZA6E
• Description: IC FLASH 512MBIT 63VFBGA
• Manufacturer: NUMONYX

Specifications of NAND512R3A2CZA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 512M (64M x 8)
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND512-A2C
6.5
Figure 15. Block erase operation
6.6
RB
I/O
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
Once the erase operation has completed the status register can be checked for errors.
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
of t
issued, refer to
Block Erase
Setup Code
BLBH4
One bus cycle is required to setup the Block Erase command
Only three bus cycles for 512-Mbit and 1-Gbit devices, or two for 128-Mbit and 256-Mbit
devices are required to input the block address. The first cycle (A0 to A7) is not
required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the last
address cycle I/O2 to I/O7 must be set to V
One bus cycle is required to issue the confirm command to start the P/E/R controller.
60h
depends on the operation that the device was performing when the command was
Table 21
Block Address
Inputs
for the values.
Confirm
Code
D0h
BLBH4
after the Reset command is issued. The value
IL
.
(Erase Busy time)
Figure
tBLBH3
Busy
15):
Read Status Register
70h
Device operations
SR0
ai07593
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