CY7C185-35SC Cypress Semiconductor Corp, CY7C185-35SC Datasheet
CY7C185-35SC
Specifications of CY7C185-35SC
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CY7C185-35SC Summary of contents
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... LOW chip enable (CE chip enable (CE tri-state drivers. This device has an automatic power down feature (CE 1 when deselected. The CY7C185 standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE inputs are both LOW and CE ...
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... V – – 130 , 40 – 0.3V, CC – 0.3V or Test Conditions T = 25 MHz 5.0V CC CY7C185 Ambient Temperature V CC 5V 10 +70 C 5V 10% – +85 C –20 –35 Min Max Min Max 2.4 2.4 0.4 0.4 2 0.3V 2 ...
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... LZCE1 LZCE2 LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either 1 2 CY7C185 ALL INPUT PULSES 90% 90% 10% 10% THÉVENIN EQUIVALENT 167 OUTPUT 1.73V -20 -35 Min Max Min Max Unit ...
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... DATA VALID 50 LOW, CE HIGH and WE LOW going HIGH or CE going LOW. The data input setup and hold timing must be referenced to the rising 1 2 CY7C185 DATA VALID t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB and WE must be LOW and CE must be HIGH 1 2 Page [+] Feedback ...
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... During this period, the IOs are in the output state and input signals must not be applied. 13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t Document #: 38-05043 Rev SCEI SCE2 t PWE t SD DATA VALID SCE1 SA t SCE2 DATA VALID IN and t HZWE CY7C185 [9,11 [11,12,13 Page [+] Feedback ...
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... Switching Waveforms (continued) Figure 6. Write Cycle No. 3(WE Controlled, OE LOW) ADDRESS DATA IO NOTE 12 t HZWE Note 14 goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state Document #: 38-05043 Rev. *D [11,12,13,14 SCE1 t SCE2 DATA VALID IN CY7C185 LZWE Page [+] Feedback ...
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... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. =25C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) CY7C185 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. =25 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
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... High High Data Out Data High Z Ordering Information Speed (ns) Ordering Code 15 CY7C185-15VI 20 CY7C185-20PXC 35 CY7C185-35SC Ordering Code Definitions Document #: 38-05043 Rev. *D Address Designators Address Name Mode A4 Deselect/Power Down A5 Deselect/Power A6 Down A7 Read A8 Write A9 Deselect A10 A11 A12 Package Name Package Type 51-85031 ...
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... Package Diagrams Figure 8. 28-pin (300-Mil) Molded SOIC (51-85026) Document #: 38-05043 Rev. *D Figure 7. 28-pin (300-Mil) PDIP (51-85014) CY7C185 51-85014 *E 51-85026 *E Page [+] Feedback ...
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... Package Diagrams (continued) Figure 9. 28-pin (300-Mil) Molded SOJ (51-85031) Document #: 38-05043 Rev. *D CY7C185 51-85031 *D Page [+] Feedback ...
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... Document History Page Document Title: CY7C185, 64-Kbit (8 K × 8) Static RAM Document Number: 38-05043 Orig. of REV. ECN NO. Issue Date Change ** 107145 09/10/01 *A 116470 09/16/02 *B 486744 See ECN *C 2263686 See ECN VKN/AESA Removed 25 ns speed bin *D 3105329 12/09/2010 Document #: 38-05043 Rev. *D Description of Change ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05043 Rev. *D All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised December 9, 2010 CY7C185 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...