CAT25020VI-G ON Semiconductor, CAT25020VI-G Datasheet - Page 9

• Manufacturer Part Number: CAT25020VI-G
• Description: IC EEPROM 2KBIT 10MHZ 8SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT25020VI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 256 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 75 ns
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hold Operation
between host and CAT25010/20/40. To pause, HOLD must
be taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state. The device will
power up into Standby mode after V
trigger level and will power down into Reset mode when
The HOLD input can be used to pause communication
The CAT25010/20/40 devices incorporate Power−On
HOLD
SCK
CS
SO
Dashed Line = mode (1, 1)
t
HD
CC
exceeds the POR
t
CD
t
HZ
Figure 11. HOLD Timing
http://onsemi.com
9
HIGH IMPEDANCE
V
POR behavior protects the device against ‘brown−out’
failure following a temporary loss of power.
state and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
CC
The CAT25010/20/40 device powers up in a write disable
After power up, the CS pin must be brought low to enter
drops below the POR trigger level. This bi−directional
t
HD
t
CD
t
LZ