CAT25640VI-G ON Semiconductor, CAT25640VI-G Datasheet - Page 4

• Manufacturer Part Number: CAT25640VI-G
• Description: IC EEPROM 64KBIT 10MHZ 8SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT25640VI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 8 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 75 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25640.
CS: The chip select input pin is used to enable/disable the
CAT25640. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress). Every communication
session between host and CAT25640 must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25640, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, the HOLD input should be tied to V
directly or through a resistor.
SCK
SO
CS
SI
t
CNH
HI−Z
t
SU
t
CSS
VALID
IN
t
t
H
WH
Figure 2. Synchronous Data Timing
CC
t
WL
, either
http://onsemi.com
t
V
t
t
RI
FI
VALID
OUT
4
t
HO
Functional Description
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
simply providing the READ command and an address.
Writing to the CAT25640, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
CAT25640 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 7. INSTRUCTION SET
The CAT25640 device supports the Serial Peripheral
Reading data stored in the CAT25640 is accomplished by
After a high to low transition on the CS input pin, the
Instruction
WRITE
WREN
WRSR
RDSR
WRDI
READ
t
CSH
t
V
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
Op−code
t
DIS
t
CS
t
CNS
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Operation
HI−Z