AT17LV010A-10PC Atmel, AT17LV010A-10PC Datasheet
AT17LV010A-10PC
Specifications of AT17LV010A-10PC
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AT17LV010A-10PC Summary of contents
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... PLCC 32-lead – TQFP ® , Virtex (1) , 20-lead PLCC and 32-lead AT17LV512A AT17LV010A Yes Yes Yes Yes – Yes ™ FPGAs, FPGA Configuration EEPROM Memory AT17LV65A AT17LV128A AT17LV256A AT17LV512A AT17LV010A AT17LV002A 3.3V and 5V System Support AT17LV002A – Yes Yes 2322G–CNFG–03/06 ...
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... RESET/OE 8 32-lead TQFP NC 1 DCLK (3) (WP1 ) RESET/ This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. This pin is only available on AT17LV010A/002A devices. 4. The nCASC feature is not available on the AT17LV65A device VCC 2 7 SER_EN ( (A2) nCASC 4 5 GND 18 SER_EN (2) 15 ...
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Figure 2-4. Block Diagram SER_EN (2) WP1 OSCILLATOR CONTROLL (3) OSCILLATOR POWER ON RESET DCLK READY Notes: 1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. The nCASC feature is ...
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... AT17LV65A/ AT17LV128A/ AT17LV256A 20 Name I/O PLCC DATA I/O 2 DCLK I 4 WP1 I – RESET nCS I 9 GND 10 nCASC READY O – SER_EN Note: 1. The nCASC feature is not available on the AT17LV65A device. AT17LV65A/128A/256A/512A/002A 4 AT17LV512A/ AT17LV010A PDIP PLCC TQFP – – AT17LV002A 20 32 PLCC TQFP ...
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DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 4.2 DCLK Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The ...
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READY Open collector reset state indicator. Driven Low during power-on reset cycle, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). 4.11 SER_EN Serial enable must be held High during FPGA loading operations. Bringing ...
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AT17A Series Reset Polarity The AT17A series configurator allows the user to program the polarity of the RESET/OE pin as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. 9. Programming Mode The programming mode is ...
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... Min Max Min V 2 0.8 0 0.8 0 2.4 2.4 0.4 0.4 2.4 2.4 0.4 0 -10 10 -10 50 100 100 100 AT17LV512A/ AT17LV010A AT17LV002A Max Min Max Min V 2 0.8 0 0.8 0 3.86 3.86 0.32 0.32 3.76 3.76 0.37 0. -10 10 -10 75 200 150 ...
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AC Waveforms nCS RESET/OE DCLK T CE DATA 16. AC Waveforms when Cascading RESET/OE nCS DCLK T CDF LAST BIT DATA T OCK nCASL 2322G–CNFG–03/06 AT17LV65A/128A/256A/512A/002A T SCE CAC T OCE T ...
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AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK ...
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AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC ...
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... For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. AT17LV65A/128A/256A/512A/002A 12 (1) AT17LV65A/ AT17LV128A/ AT17LV256A θ [°C/W] JC θ (2) [°C/W] JA θ [°C/ θ (2) [°C/ θ [°C/W] JC θ (2) [°C/W] JA θ [°C/W] – JC θ (2) [°C/W] – JA AT17LV512A/ AT17LV010A AT17LV002A 37 107 – 15 – 50 2322G–CNFG–03/06 ...
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... The 8-lead LAP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the 8-lead package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040 datasheet available on the Atmel web site for more information. 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) ...
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... Standard Package Options Memory Size (2)(7) 64-Kbit (7) 128-Kbit (3)(7) 256-Kbit AT17LV512A-10PC (4)(7) 512-Kbit AT17LV010A-10PC AT17LV010A-10QC (5)(7) 1-Mbit AT17LV002A-10QC (6)(7) 2-Mbit 22.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size (4)(7) 512-Kbit (5)(7) 1-Mbit AT17LV010A-10PU (4)(7) 2-Mbit Notes: 1. Currently, there are two types of low-density configurators. The new version will be identified by a “B” after the datacode. The “ ...
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Packaging Information 23.1 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L ...
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PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...
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