AT17LV512-10PI Atmel, AT17LV512-10PI Datasheet
AT17LV512-10PI
Specifications of AT17LV512-10PI
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AT17LV512-10PI Summary of contents
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... Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. ® ® ™ FLEX , APEX ® ® , Virtex FPGAs Table 1-1. The AT17LV series FPGA Configuration EEPROM Memory AT17LV65 AT17LV128 AT17LV256 AT17LV512 AT17LV010 AT17LV002 AT17LV040 3.3V and 5V System Support 2321I–CNFG–2/08 ...
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... The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not available for the AT17LV512/010/002 devices possible to use an 8-lead LAP package instead. 2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the AT17LV512/010/002 devices. ...
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... Note: 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 20-lead PLCC CLK 4 (2) (WP1 ) NC 5 (1) (WP ) RESET/OE 6 (2) (WP2 ) This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the AT17LV65 device. (1) 20-lead SOIC NC 1 DATA CLK RESET/ ...
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... Figure 2-6. Notes: Figure 2-7. Note: AT17LV65/128/256/512/010/002/040 4 (1) 20-lead SOIC DATA CLK RESET/ This pinout only applies to AT17LV512/010/002 devices. 2. The CEO feature is not available on the AT17LV65 device. 44 TQFP (1) (WP1 ) This pin is only available on AT17LV002 devices. 20 VCC SER_EN CEO GND READY 2321I–CNFG–2/08 ...
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... Figure 2-8. Block Diagram SER_EN (2) WP1 (2) WP2 POWER ON RESET Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the AT17LV65 device. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 (2) (1) READY 5 ...
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... DATA I CLK WP1 I – – RESET/ WP2 GND 5 10 CEO READY O – – SER_EN Note: 1. The CEO feature is not available on the AT17LV65 device. AT17LV65/128/256/512/010/002/040 6 AT17LV512/ AT17LV010 8 20 DIP SOIC LAP PLCC SOIC – – 5 – – 7 – – – – 15 – ...
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... WP2 WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010 devices. 4.7 CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver ...
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... FPGA mode pins. In Master mode, the FPGA automatically loads the config- uration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil- inx applications. 6. Control of Configuration Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory ...
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... The AT17LV series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 µA of current at 3.3V (100 µA for the AT17LV512/010 and 200 µA for the AT17LV002/040). The output remains in a high-impedance state regardless of the state of the OE input. ...
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Absolute Maximum Ratings* Operating Temperature................................... -40° +85° C Storage Temperature .................................... -65° +150° C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering ...
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... Max Min Max Min V 2 0.8 0 0.8 0 2.4 2.4 0.4 0.4 2.4 2.4 0.4 0 -10 10 -10 50 100 100 100 AT17LV512/ AT17LV002/ AT17LV010 AT17LV040 Max Min Max Min V 2 0.8 0 0.8 0 3.86 3.86 0.32 0.32 3.76 3.76 0.37 0. -10 10 -10 ...
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AC Waveforms CE RESET/OE CLK T CE DATA 16. AC Waveforms when Cascading RESET/OE CE CLK T DATA LAST BIT T CEO AT17LV65/128/256/512/010/002/040 12 T SCE CAC CDF T OCK OCE T ...
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... Float delays are measured with loads. Transition is measured ± 200 mV from steady-state active levels. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Min Max Min Max Min AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Min Max Min Max Min Industrial Max Min Max Units ...
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... Float delays are measured with loads. Transition is measured ± 200 mV from steady-state active levels. AT17LV65/128/256/512/010/002/040 14 AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Min Max Min Max Min 12.5 12.5 AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Min Max Min Max Min Industrial Max Min Max Units ...
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... Thin Plastic Quad Flat 44A Package (TQFP) Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 (1) AT17LV65/ AT17LV128/ AT17LV512/ AT17LV256 AT17LV010 θ [° C/ θ JA 115.71 (2) [° C/W] θ ...
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... Plastic J-leaded Chip Carrier (PLCC) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) AT17LV65/128/256/512/010/002/040 16 AT17LV65A-10PC Special Pinouts = 65K A = Altera = 128K Blank = Xilinx /Atmel/ Other = 256K = 512K = Package Type Package Temperature C = 8CN4 C = Commercial ...
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... AT17LV65-10JI AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI AT17LV512-10PC AT17LV512-10JC AT17LV512-10PI AT17LV512-10JI AT17LV010-10PC AT17LV010-10JC AT17LV010-10PI AT17LV010-10JI AT17LV002-10JC AT17LV002-10JI (2)(3) Package Operation Range 8P3 Commercial 8S1 (0° 70° C) 20J 8P3 Industrial 8S1 (-40° 85° C) ...
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... AT17LV002-10TQU (1) 4-Mbit AT17LV040-10TQU Note: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. AT17LV65/128/256/512/010/002/040 18 Ordering Code AT17LV256-10CU AT17LV256-10JU AT17LV256-10NU AT17LV256-10PU AT17LV256-10SU AT17LV512-10CU AT17LV512-10JU AT17LV010-10CU AT17LV010-10JU AT17LV010-10PU AT17LV002-10CU AT17LV002-10JU AT17LV002-10SU Package Operation Range 8CN4 20J 8S1 8P3 20S2 8CN4 20J ...
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... TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm Package Drawing Contact: packagedrawings@atmel.com 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 D Pin1 Corner TITLE 8CN4, 8-lead ( 1.04 mm Body), Lead Pitch 1.27mm, ...
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PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with ...
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SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 ...
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PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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SOIC 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23 ...
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TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
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Revision History Revision Level – Release Date H – March 2006 I – February 2008 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 History Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI. Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information. 25 ...
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