EPC1441LC20N Altera, EPC1441LC20N Datasheet - Page 16

• Manufacturer Part Number: EPC1441LC20N
• Description: IC CONFIG DEVICE 440KBIT 20-PLCC
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC1441LC20N

• Programmable Type: OTP
• Memory Size: 440kb
• Voltage - Supply: 3 V ~ 3.6 V, 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-PLCC
• Function: Configuration Device
• Frequency (max): 16.7MHz
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: PLCC
• Memory Type: Flash
• Supply Voltage Range: 3V To 5.25V
• Memory Case Style: LCC
• No. Of Pins: 20
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Digital Ic Case Style: LCC
• For Use With: PLMJ1213 - PROGRAMMER ADAPTER 20 PIN J-LEAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1371-5; EPC1441LC20N

4–16 Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Timing Information
Figure 4–5. Timing Waveform Using a Configuration Device
Note to
(1) The EPC2 device will drive DCLK low and DATA high after configuration. The EPC1 and EPC1441 device will drive DCLK low and tri-state DATA
Table 4–8. Timing Parameters when Using EPC2 devices at 3.3 V
Configuration Handbook (Complete Two-Volume Set)
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
Note to
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
POR
OEZX
CE
DSU
DH
CO
CDOE
CLK
MCH
MCL
SCH
SCL
CASC
CCA
OEW
OEC
NRCAS
Symbol
after configuration.
Figure
Table
nINIT_CONF or VCC/nCONFIG
POR delay
OE high to DATA output enabled
OE high to first rising edge on DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK to DATA out
DCLK to DATA enable/disable
DCLK frequency
DCLK high time for the first device in the configuration chain
DCLK low time for the first device in the configuration chain
DCLK high time for subsequent devices
DCLK low time for subsequent devices
DCLK rising edge to nCASC
nCS to nCASC cascade delay
OE low pulse width (reset) to guarantee counter reset
OE low (reset) to DCLK disable delay
OE low (reset) to nCASC delay
4–5:
4–8:
nCS/CONF_DONE
OE/nSTATUS
INIT_DONE
Figure 4–5
Table 4–8
(1)
User I/O
DCLK
DATA
t
OEZX
defines the timing parameters when using EPC2 devices at 3.3 V.
shows the timing waveform when using a configuration device.
t
CO
Tri-State
t
t
Parameter
POR
DSU
D
0
D
t
CL
1
D
t
2
DH
D
t
CH
3
D
n
Tri-State
Min
100
—
—
—
30
—
—
40
40
40
40
—
—
—
—
0
5
© December 2009
User Mode
Typ
7.7
—
—
—
—
—
—
—
65
65
—
—
—
—
—
—
—
(1)
Max
12.5
200
300
100
100
80
—
—
30
30
—
—
25
15
—
30
30
Timing Information
Altera Corporation
Units
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns