AT17C512-10CI Atmel, AT17C512-10CI Datasheet - Page 4

• Manufacturer Part Number: AT17C512-10CI
• Description: IC SRL CONFIG EEPROM 512K 8LAP
• Manufacturer: Atmel

Specifications of AT17C512-10CI

• Programmable Type: Serial EEPROM
• Memory Size: 512kb
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-LAP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Programming Mode
Standby Mode
Pin Configurations
4
PDIP/
LAP
Pin
8
1
2
3
4
5
AT17C512/010/LV512/010
PLCC
Pin
20
10
2
4
5
6
7
8
RESET/OE
Name
DATA
WP1
WP2
GND
CLK
CE
reference the “Programming Specification for Atmel’s FPGA Configuration EEPROMs”
application note.
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. See the “Programming
Specification for Atmel’s FPGA Configuration EEPROMs” application note for further
information. The AT17C parts are read/write at 5V nominal. The AT17LV parts are
read/write at 3.3V nominal.
The AT17C/LV512/010 Series Configurator enters a low-power standby mode when-
ever CE is asserted High. In this mode, the Configurator consumes less than 0.5 mA of
current at 5V. The output remains in a high impedance state regardless of the state of
the OE input.
I/O
I/O
I
I
I
I
I
Description
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations. See the “Programming Specification” application
note for more details.
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE
and RESET/OE inputs enables the data output driver. A High level on RESET/OE
resets both the address and bit counters. The logic polarity of this input is
programmable as either RESET/OE or RESET/OE. This document describes the
pin as RESET/OE.
WRITE PROTECT (2). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations. See the “Programming Specification” application
note for more details.
Chip Enable input. Used for device selection. A Low level on both CE and OE
enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin
will not enable/disable the device in the 2-wire Serial Programming Mode (i.e., when
SER_EN is Low).
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is
recommended.