AT17LV040A-10BJI Atmel, AT17LV040A-10BJI Datasheet
AT17LV040A-10BJI
Specifications of AT17LV040A-10BJI
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AT17LV040A-10BJI Summary of contents
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... Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version • In-System Programmable (ISP) via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX, APEX ® ® Devices, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200, Spartan Motorola MPA1000 FPGAs • ...
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Pin Configuration Figure 2-1. Figure 2-2. Figure 2-3. Notes: AT17LV65A/128A/256A/512A/002A 2 8-lead PDIP DATA DCLK (1) (WP ) RESET/OE nCS 20-lead PLCC DCLK 4 (2) WP1 (1) (WP ) RESET/OE 8 32-lead TQFP NC ...
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Figure 2-4. Block Diagram SER_EN (2) WP1 OSCILLATOR CONTROLL (3) OSCILLATOR POWER ON RESET DCLK READY Notes: 1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. The nCASC feature is ...
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Device Description The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configura- tion process and retrieve data from the configuration EEPROM without ...
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DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 4.2 DCLK Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The ...
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READY Open collector reset state indicator. Driven Low during power-on reset cycle, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). 4.11 SER_EN Serial enable must be held High during FPGA loading operations. Bringing ...
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AT17A Series Reset Polarity The AT17A series configurator allows the user to program the polarity of the RESET/OE pin as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. 9. Programming Mode The programming mode is ...
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DC Characteristics V = 3.3V ± 10% CC Symbol Description V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage ( Low-level Output Voltage ( High-level Output Voltage (I ...
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AC Waveforms nCS RESET/OE DCLK T CE DATA 16. AC Waveforms when Cascading RESET/OE nCS DCLK T CDF LAST BIT DATA T OCK nCASL 2322G–CNFG–03/06 AT17LV65A/128A/256A/512A/002A T SCE CAC T OCE T ...
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AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK ...
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AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC ...
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... Plastic Leaded Chip Carrier (PLCC) Thin Plastic Quad Flat Package 32A (TQFP) 44J Plastic Leaded Chip Carrier (PLCC) Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. AT17LV65A/128A/256A/512A/002A 12 (1) AT17LV65A/ AT17LV128A/ AT17LV256A θ ...
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... The 8-lead LAP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the 8-lead package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040 datasheet available on the Atmel web site for more information. 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) ...
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... Use 512-Kbit density parts to replace Altera EPC1441. 5. Use 1-Mbit density parts to replace Altera EPC1 6. Use 2-Mbit density parts to replace Altera EPC2. Atmel AT17LV002A devices do not support JTAG programming; Atmel AT17LV002A devices use a 2-wire serial interface for in-system programming. 7. For operating voltage of 5V ±10%, please refer to the 5V ±10% AC and DC Characteristics. ...
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Packaging Information 23.1 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L ...
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PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...