NSBMC096VF-33 National Semiconductor, NSBMC096VF-33 Datasheet - Page 15

• Manufacturer Part Number: NSBMC096VF-33
• Description: IC CONTROLLER BURST MEM 132-PQFP
• Manufacturer: National Semiconductor

Specifications of NSBMC096VF-33

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *NSBMC096VF-33

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
AC Timing Parameters
Note 1 Derate the given delays by 0 006 ns per pF of load in excess of 50 pF
Note 2 t
silicon
1
2
3
4
5
6
7
8
9
Signal output delays are measured relative to PCLK (except as indicated) using a 50 pF load
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ADSU
ADH
SU
H
BLSU
BLH
RZH
RHL
RLH
RHZ
ARA
RAH
CAV
CAH
DRAH
RSHL
RSLH
CHL
CLH
BHL
BLH
BSV
BSH
WEHL
WELH
BCAH
BCAV
LEHL
LELH
RFA
RFH
RFHL
RFLH
M
e
PCLK High duration when configuration bit 18
Address Strobe Setup Time
Address Strobe Hold Time
Synchronous Input Setup
Synchronous Input Hold
BLAST Input Setup
BLAST Input Hold
READY 3-state to Valid Delay Relative to PCLK
READY Synchronous Assertion Delay
READY Synchronous De-assertion Delay
READY Valid to 3-state Delay Relative to PCLK
Address Input to Row Address Output Delay (Note 1)
PCLK to Column Address Hold
DRAM Row Address Hold (Note 2)
PCLK to RAS Asserted Delay (Note 1)
PCLK to RAS De-asserted Delay (Note 1)
PCLK to CAS Asserted Delay (Note 1)
PCLK to CAS De-asserted Delay (Note 1)
PCLK to Buffer Control Asserted Delay (Note 1)
PCLK to Buffer Control De-asserted Delay (Note 1)
PCLK to Bank Select Valid Time (Note 1)
PCLK to Bank Select Hold Time (Note 1)
PCLK to Write Enable De-asserted Delay (Note 1)
PCLK to Latch Enable De-assertion
PCLK to Row Address Valid (Refresh)
PCLK to Row Address Hold (Refresh)
REFRESH Synchronous Assertion Delay
REFRESH Synchronous De-assertion Delay
PCLK or PCLK to Row Address Hold
PCLK or PCLK to Column Address Valid (Note 1)
PCLK to Write Enable Asserted Delay (Note 1)
PCLK to Column Address Hold Time (Burst) (Note 1)
PCLK to Column Address Valid Delay (Burst) (Note 1)
PCLK to Latch Enable Assertion
Description
(Unless otherwise stated V
e
0 t
M
e
PCLK cycle time
15
CC
e
5 0V
e
Min
t
1
14
14
14
M-4
4
5
4
4
5
16 MHz
(PCLK frequency)
g
5% 0 C
Max
29
26
25
27
23
40
38
29
26
23
20
26
23
26
31
29
23
20
38
20
20
3
3
3
k
for configuration bit 18
T
Min
t
M-4
12
12
12
A k
4
4
4
5
5
25 MHz
70 C )
Max
24
21
20
22
19
33
31
24
21
19
16
21
19
21
25
23
19
16
31
16
16
3
3
3
t
Min
M-3
9
9
9
4
4
4
4
4
e
33 MHz
1 Timing for Rev AB
Max
19
17
16
17
15
26
25
19
17
15
13
17
15
17
20
19
15
13
25
13
13
3
3
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns