VIPER100ASPTR-E STMicroelectronics, VIPER100ASPTR-E Datasheet - Page 13
Manufacturer Part Number
IC SWIT PWM SMPS CM POWERSO10
Specifications of VIPER100ASPTR-E
90 ~ 200kHz
Voltage - Input
8 ~ 15 V
Voltage - Output
25°C ~ 125°C
Package / Case
PowerSO-10 Exposed Bottom Pad
Number Of Outputs
700 V (Min)
90 KHz to 110 KHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be also used as the compensation network. In this case, the regulation loop bandwidth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of
performance compensation network together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the V
This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA.
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.
Transconductance Error Amplifier
The VIPer100A-E/ASP-E includes a transconductance error amplifier. Transconductance Gm is
the change in output current (I
The output impedance Z
This last equation shows that the open loop gain A
An impedance Z can be connected between the COMP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):
The error amplifier frequency response is reported in
resistance connected on the COMP pin. The unloaded transconductance error amplifier shows
an internal Z
pin to achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This configuration is illustrated in
As shown in
avoid any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%.
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
is defined by specification, but Z
= Gm x Z(S)
is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).
value for VIPer100A-E/ASP-E is 1.5 mA/V typically.
of about 330K . More complex impedance can be connected on the COMP
(see Figure 18)
an additional noise filtering capacitor of 2.2nF is generally needed to
at the output of this amplifier (COMP pin) can be defined as:
shows a typical application of this function, with a latched
) versus change in input voltage (V
shows such a configuration. Note: R1 and C2 build the
voltage is oscillating between V
and therefore A
(see Figure 17)
can be related to G
can be used. It mixes a high
are subject to large tolerances.
for different values of a simple
5 Operation Description