VIPER53DIP-E STMicroelectronics, VIPER53DIP-E Datasheet - Page 15
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VIPER53DIP-E
Manufacturer Part Number
VIPER53DIP-E
Description
IC OFFLINE SWIT PWM CM OTP 8DIP
Manufacturer
STMicroelectronics
Series
VIPER™r
Type
Pulse Width Modulator Controllerr
Datasheets
1.VIPER53SPTR-E.pdf
(36 pages)
2.VIPER53DIP-E.pdf
(7 pages)
3.VIPER53DIP-E.pdf
(24 pages)
Specifications of VIPER53DIP-E
Output Isolation
Isolated
Frequency Range
93 ~ 300kHz
Voltage - Input
8.4 ~ 19 V
Voltage - Output
620V
Power (watts)
30W
Operating Temperature
25°C ~ 125°C
Package / Case
8-DIP (0.300", 7.62mm)
Current, Supply
9 mA
Frequency, Oscillator
100 kHz
Package Type
DIP-8
Regulator Type
Switching
Resistance, Thermal, Junction To Case
20 °C/W
Temperature, Operating, Range
-40 to +150 °C
Time, Fall
100 ns
Time, Rise
50 ns
Voltage, Supply
13 V
Power Switch Family
VIPer53DIP
Input Voltage
0 to 19V
Power Switch On Resistance
900mOhm
Output Current
1.6A
Number Of Outputs
Single
Mounting
Through Hole
Supply Current
9mA
Operating Temperature (min)
-40C
Operating Temperature (max)
150C
Operating Temperature Classification
Automotive
Pin Count
8
Mounting Style
Through Hole
For Use With
497-8435 - BOARD EVAL FOR VIPER53 28W497-6458 - BOARD EVAL BASED ON VIPER53-E497-6262 - BOARD REF SGL VIPER53 90-264VAC497-5866 - EVAL BOARD 24W NEG OUT VIPER53E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6171-5
Figure 16: Standby Mode Implementation
actually an equivalent number of switching pulses
per second, rather than a fixed switching
frequency, as the device is working in burst mode.
As long as the power remains below P
output of the regulation loop remains stuck at
V
Its “density” increases (i.e. the number of missing
cycles decreases) as the power approaches P
and resumes finally normal operation at point 1.
The hysteresis cannot be seen on the switching
frequency, but the COMP pin voltage which
passes brutally at that power level from point 3 to
point 1.
The power points value P
defined by the following formulas:
P
P
Where Ip(V
current corresponding to a compensation voltage
of V
that the power point P
going into burst mode doesn’t depend on the input
voltage.
The standby frequency F
F
The ratio between the nominal switching frequency
and the standby one can be as high as 4,
depending on the Lp value and input voltage.
RST
STBY
SWstby
Minimum
turn on
COMPsd
350ns
600ns
P
ton
P
P
COMPbl
STBY
RST
IN
=
=
1
-- - F
2
=
1
-- - F
2
and the converter works in burst mode.
V
V
P
-------------- F
P
COMPsd
COMPoff
(1V), that is to say about 250 mA. Note
3
COMPbl
STBY
SWnom
RST
SW nom
F
SWstby
3
) is the peak Power MOSFET
SWnom
tb
Ip
2
V
STBY
1
2
COMPbl
+
V
SWstb y
td
COMPbl
where the converter is
RST
2
1
V
is given by:
2
IN
F
and P
SWnom
Lp
------
L p
1
2
1
STBY
RST
V
COMP
F
SW
RST
are
the
HIGH VOLTAGE START-UP CURRENT
SOURCE
An integrated high voltage current source provides
a bias current from the DRAIN pin during the start-
up phase. This current is partially absorbed by
internal control circuits in standby mode with
reduced consumption and also supplies the
external capacitor connected to the VDD pin. As
soon as the voltage on this pin reaches the high
voltage threshold V
device turns into active mode and starts switching.
The start-up current generator is switched off, and
the converter should normally provide the needed
current on the VDD pin through the auxiliary
winding of the transformer, as shown on figure 14
or 15.
The external capacitor C
be sized according to the time needed by the
converter to start-up, when the device starts
switching. This time tss depends on many
parameters, among which transformer design,
output
compensation network implemented on the COMP
pin and possible secondary feedback circuit. The
following formula can be used for defining the
minimum capacitor needed:
C
Figure 17 shows a typical start-up event. V
starts from 0 V with a charging current I
about 9 mA. When about V
Figure 17: Startup Waveforms
VDD
V
I
I
V
V
DDch2
DDch1
V
I
DDreg
DDsd
DD
DD
I
DDst
DD1
I
---------------------- -
DD1
V
capacitors,
DDhyst
tss
tsu
tss
DDon
VIPer53DIP / VIPer53SP
soft
VDD
of the UVLO logic, the
DDoff
on the VDD pin must
start
is reached, the
feature
DDch1
15/24
and
t
DD
t
at