LNK564DN Power Integrations, LNK564DN Datasheet - Page 7

IC OFFLINE SWIT OTP HV 8SOIC

LNK564DN

Manufacturer Part Number
LNK564DN
Description
IC OFFLINE SWIT OTP HV 8SOIC
Manufacturer
Power Integrations
Series
LinkSwitch®-LPr
Datasheet

Specifications of LNK564DN

Output Isolation
Isolated
Frequency Range
93 ~ 107kHz
Voltage - Output
700V
Power (watts)
3W
Operating Temperature
-40°C ~ 150°C
Package / Case
8-SOIC (0.154", 3.90mm Width) 7 leads
Input / Supply Voltage (max)
265 VAC
Input / Supply Voltage (min)
85 VAC
Duty Cycle (max)
70 %
Switching Frequency
100 kHz
Supply Current
160 uA
Operating Temperature Range
- 40 C to + 150 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 7. Recommended Circuit Board Layout for LinkSwitch-LP using D Package (Assumes a HVDC Input Stage).
Output Diode
For best performance, the area of the loop connecting the
secondary winding, the output diode and the output fi lter
capacitor should be minimized. In addition, suffi cient copper
area should be provided at the anode and cathode terminals
of the diode for heat sinking. A larger area is preferred at the
quiet cathode terminal. A large anode area can increase high-
frequency radiated EMI.
Quick Design Checklist
As with any power supply design, all LinkSwitch-LP designs
should be verifi ed on the bench to make sure that component
specifi cations are not exceeded under worst-case conditions. The
following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that V
2. Maximum drain current – At maximum ambient
650 V at the highest input voltage and peak (overload) output
power. A 50 V margin to the 700 V BV
margin for design variation, especially in Clampless designs.
temperature, maximum input voltage and peak output
TOP VIEW
T r a n s f o r m e r
Output Filter
Capacitor
DSS
DS
specifi cation gives
does not exceed
OUT
DC
+
-
C
BP
FB
BP
3. Thermal Check – At specified maximum output
Design Tools
Up-to-date information on design tools can be found at the
Power Integrations web site: www.powerint.com.
D
(overload) power, verify drain current waveforms for any
signs of transformer saturation and excessive leading-edge
current spikes at startup. Repeat under steady state conditions
and verify that the leading-edge current spike event is below
I
maximum DRAIN current should be below the specifi ed
absolute maximum ratings.
power, minimum input voltage and maximum ambient
temperature, verify that the temperature specifi cations
are not exceeded for LinkSwitch-LP, transformer, output
diode and output capacitors. Enough thermal margin
should be allowed for part-to-part variation of the R
LinkSwitch-LP as specifi ed in the data sheet. Under low line
and maximum power, a maximum LinkSwitch-LP SOURCE pin
temperature of 100 °C is recommended to allow for
these variations.
LIMIT(MIN)
at the end of the t
S
S
S
S
Maximize hatched copper
areas (
heatsinking
LEB(MIN)
-
LNK562-564
HV DC
INPUT
) for optimum
. Under all conditions, the
+
PI-4582-021407
Input Filter
Capacitor
DS(ON)
Rev. H 11/08
7
of

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