LTC4012IUF#PBF Linear Technology, LTC4012IUF#PBF Datasheet - Page 24

• Manufacturer Part Number: LTC4012IUF#PBF
• Description: IC BATT CHRGR MC HI-EFF 20-QFN
• Manufacturer: Linear Technology

Specifications of LTC4012IUF#PBF

• Function: Charge Management
• Battery Type: Multi-Chemistry
• Voltage - Supply: 6 V ~ 28 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC4012/
LTC4012-1/LTC4012-2
applications inForMation

The LTC4012 can be soft-started with the compensation
capacitor on the ITH pin. At start-up, ITH will quickly rise
to about 0.25V, then ramp up at a rate set by the com-
pensation capacitor and the 40µA ITH bias current. The
full programmed charge current will be reached when ITH
reaches approximately 2V. With a 0.1µF capacitor, the time
to reach full charge current is usually greater than 1.5ms.
This capacitor can be increased if longer start-up times
are required, but loop bandwidth and dynamic response
will be reduced.
INTV
Bypass the INTV
ESR X5R or X7R ceramic capacitor with a value of 0.47µF
or larger. The capacitor used to build the BOOST supply
(C2 in Figure 11) can serve as this bypass. Do not draw
more than 30mA from this regulator for the host system,
governed by IC power dissipation.
Calculating IC Power Dissipation
The user should ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4012 package (θ
37°C/W, provided the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in the
application will depend on forced air cooling and other heat
sinking means, especially the amount of copper on the PCB
to which the LTC4012 is attached. The following formula
may be used to estimate the maximum average power dis-
sipation P
upon the gate charge of the external MOSFETs. This gate
charge, which is a function of both gate and drain voltage
swings, is determined from specifications or graphs in the
manufacturer’s data sheet. For the equation below, find the
gate charge for each transistor assuming 5V gate swing and
a drain voltage swing equal to the maximum V
Maximum LTC4012 power dissipation under normal op-
erating conditions is then given by:
P
– 5I
D
DD
= DCIN(3mA + I
DD
Regulator Output
D
(in watts) of the LTC4012, which is dependent
DD
regulator output to GND with a low
DD
+ 665kHz(Q
TGATE
CLP
+ Q
voltage.
BGATE
JA
) is
))
where:
PCB Layout Considerations
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4012 is essential. Refer
to Figure 12. For maximum efficiency, the switch node
rise and fall times should be minimized. The following
PCB design priority list will help insure proper topology.
Layout the PCB using this specific order.
1. Input capacitors should be placed as close as possible
2. Place the LTC4012 close to the switching FET gate
GND
V
IN
I
Q
Q
DD
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to IC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
TGATE
BGATE
= Average external INTV
= Gate charge of external top FET in Coulombs
= Gate charge of external bottom FET in
C
Figure 12. High Speed Switching Path
SWITCHING GROUND
IN
Coulombs
CIRCULATING
FREQUENCY
SWITCH NODE
HIGH
PATH
DD
L1
load current, if any
D1
R
C
OUT
SENSE
4012 F12
+
V
BAT
BAT
ANALOG
GROUND
SYSTEM
GROUND
4012fa