MAX17435ETG+ Maxim Integrated Products, MAX17435ETG+ Datasheet - Page 25

• Manufacturer Part Number: MAX17435ETG+
• Description: IC SMBUS BATT CHARGER 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17435ETG+

• Function: Charge Management
• Battery Type: Multi-Chemistry
• Voltage - Supply: 8 V ~ 26 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Product: Charge Management
• Operating Supply Voltage: 7 V to 26 V
• Supply Current: 1.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Charge Safety Timers: Yes
• Temperature Monitoring: Yes
• Uvlo Stop Threshold: 3.9 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The high-side driver (DHI) swings from LX to 5V above LX
(BST) and has a typical impedance of 1.5I sourcing and
0.8I sinking. The low-side driver (DLO) swings from DLOV
to ground and has a typical impedance of 3I sinking and
3I sourcing. This helps prevent DLO from being pulled
up when the high-side switch turns on due to capacitive
coupling from the drain to the gate of the low-side MOSFET.
This places some restrictions on the MOSFETs that can be
used. Using a low-side MOSFET with smaller gate-to-drain
capacitance can prevent these problems.
Choose the n-channel MOSFETs according to the maxi-
mum required charge current. Low-current applications
usually require less attention. The high-side MOSFET
(N1) must be able to dissipate the resistive losses plus
the switching losses at both V
Calculate both these sums.
Ideally, the losses at V
to losses at V
the losses at V
losses at V
Conversely, if the losses at V
higher than the losses at V
size of N1. If DCIN does not vary over a wide range, the
minimum power dissipation occurs where the resistive
losses equal the switching losses. Choose a low-side
MOSFET that has the lowest possible on-resistance
(R
or two 8-pin SO, DPAK, or D
priced. Make sure that the DLO gate driver can supply
sufficient current to support the gate charge and the
current injected into the parasitic gate-to-drain capacitor
caused by the high-side MOSFET turning on; otherwise,
cross-conduction problems can occur. Select devices
that have short turn-off times, and make sure that:
Failure to do so could result in efficiency-reducing shoot-
through currents.
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to resistance occurs at the
minimum supply voltage:
DS(ON)
N2(t
PD(High - side)
N1(t
), comes in a moderate-sized package (i.e., one
DOFF(MAX)
DCIN(MAX)
DOFF(MAX)
DCIN(MAX)
DCIN(MIN)
______________________________________________________________________________________
) - N1(t
, consider increasing the size of N1.
=
MOSFET Power Dissipation
DCIN(MIN)



) - N2(t
V
V
with lower losses in between. If
are significantly higher than the
BATT
DCIN
IN(MIN)
DON(MIN)
Design Procedure
DCIN(MAX)
2
DCI(MIN)
DON(MIN)
 
 


PAK), and is reasonably
I
should be roughly equal
MOSFET Selection
LOAD
, consider reducing the
2
) < 40ns, and



2
and V
) < 40ns
are significantly
×
R
DS(ON)
DCIN(MAX)
Low-Cost SMBus Chargers
.
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages. However,
the R
dissipation limits often limits how small the MOSFET can
be. The optimum occurs when the switching (AC) losses
equal the conduction (R
in the high-side MOSFET can become an insidious
heat problem when maximum AC adapter voltages are
applied, due to the squared term in the CV
loss equation. If the high-side MOSFET that was chosen
for adequate R
extraordinarily hot when subjected to V
choose a MOSFET with lower losses. Calculating the
power dissipation in N1 due to switching losses is
difficult since it must allow for difficult quantifying factors
that influence the turn-on and turn-off times. These
factors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute
for breadboard evaluation, preferably including a
verification using a thermocouple mounted on N1:
where C
and I
(3.3A sourcing and 5A sinking).
For the low-side MOSFET (N2), the worst-case power
dissipation always occurs at maximum input voltage:
The charge current, ripple, and operating frequency
(off-time) determine the inductor characteristics. For
optimum efficiency, choose the inductance according to
the following equation:
This sets the ripple current to 1/3 the charge current and
results in a good balance between inductor size and
efficiency. Higher inductor values decrease the ripple
current. Smaller inductor values require high saturation
current capabilities and degrade efficiency.
Due to the minimum t
crossing detection, higher inductor values are desired for
proper operation for a design with low input voltage and
high output voltage, especially for MAX17535.
PD(HS_Switching)
PD(Low - side)
GATE
DS(ON)
RSS
is the peak gate-drive source/sink current
L = V
is the reverse transfer capacitance of N1
required to stay within package power-
DS(ON)
High-Frequency,
BATT
=
=



1-
V
at low supply voltages becomes
OFF
DCIN(MAX)



DS(ON)
O t
V
V
BATT
DCIN
OFF
blanking effect upon zero-
/(0.3 x I
) losses. Switching losses
 
 




Inductor Selection

2
I
2 I
LOAD
×
×
C
2
GATE
CHG
RSS



2
×
)
IN(MAX)
×
2
f
SW
R
f switching-
DS(ON)
×
I
LOAD
, then
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