LTC4002EDD-4.2#PBF Linear Technology, LTC4002EDD-4.2#PBF Datasheet - Page 14
![IC CHARGER BATTERY LI-ION 10-DFN](/photos/6/59/65943/10-dfn_pkg_sml.jpg)
LTC4002EDD-4.2#PBF
Manufacturer Part Number
LTC4002EDD-4.2#PBF
Description
IC CHARGER BATTERY LI-ION 10-DFN
Manufacturer
Linear Technology
Type
Battery Chargerr
Datasheet
1.LTC4002EDD-4.2PBF.pdf
(16 pages)
Specifications of LTC4002EDD-4.2#PBF
Function
Charge Management
Battery Type
Lithium-Ion (Li-Ion)
Voltage - Supply
4.7 V ~ 22 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-WFDFN Exposed Pad
Output Voltage
4.2V
Operating Supply Voltage (min)
4.7V
Operating Supply Voltage (max)
22V
Operating Temp Range
-40C to 85C
Package Type
DFN
Mounting
Surface Mount
Pin Count
10
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APPLICATIO S I FOR ATIO
LTC4002
Next, choose the P-channel MOSFET. The Si6435ADQ in
a TSSOP-8 package with R
(max) offers a small solution. The maximum power dissi-
pation with V
temperature is:
C
85°C. The output capacitor is chosen for an ESR similar to
the battery impedance of about 100mΩ. The ripple voltage
on the BAT pin is:
C1: Taiyo Yuden TMK325BJ106MM
C2: Taiyo Yuden JMK325BJ226MM
L1: TOKO B952AS-6R8N
The Schottky diode D2 shown in Figure 2 conducts current
when the pass transistor is off. In a low duty cycle case, the
current rating should be the same or higher than the
charge current. Also it should withstand reverse voltage as
high as V
14
IN
T
P
V
is chosen for an RMS current rating of about 0.8A at
J
D
OUT RIPPLE
= 50°C + (0.099W)(65°C/W) = 56.5°C
=
(
(
1 5
IN
.
.
A
IN
)
)
2
=
(
=
= 5V and V
55
5
(
∆
V
U
0 96
m
I
.
L MAX
Ω
(
)( )
A
U
2
2
4
)
(
DS(ON)
)
V
0 1
(
ESR
.
BAT
CHARGE
STATUS
=
Ω
0 099
)
)
= 4V at 50°C ambient
= 42mΩ (nom), 55mΩ
.
=
W
48
Figure 2. 1.5A Single Cell Li-Ion Battery Charger
BAT
W
mV
R1
2k
R
2.2k
U
C
C
0.47µF
C3
0.1µF
CER
C
5
1
CHRG
COMP
LTC4002ES8-4.2
NTC
8
T
V
10k
NTC
CC
2
SENSE
GND
GATE
Board Layout Suggestions
When laying out the printed circuit board, the following
considerations should be taken to ensure proper opera-
tion of the LTC4002.
GATE pin rise and fall times are 20ns and 50ns respectively
(with C
diode, pass transistor and the input bypass capacitor
traces should be kept as short as possible. The positive
side of the input capacitor should be close to the source of
the P-channel MOSFET; it provides the AC current to the
pass transistor. The connection between the catch diode
and the pass transistor should also be kept as short as
possible. The SENSE and BAT pins should be connected
directly to the sense resistor (Kelvin sensing) for best
charge current accuracy. Avoid routing the NTC PC board
trace near the MOSFET switch to minimize coupling switch-
ing noise into the NTC pin.
The compensation capacitor connected at the COMP pin
should return to the ground pin of the IC or as close to it
as possible. This will prevent ground noise from disrupt-
ing the loop stability. The ground pin also works as a heat
sink, therefore use a generous amount of copper around
the ground pin. This is especially important for high V
and/or high gate capacitance applications.
BAT
4
NTC: DALE NTHS-1206N02
3
7
6
5V TO 22V
GATE
V
IN
M1
Si6435ADQ
R
68mΩ
L1
6.8µH
D1
B330
SENSE
C2
22µF
CER
= 2000pF). To minimize radiation, the catch
+
4002 F02
4.2V
Li-Ion
BATTERY
C1
10µF
CER
D2
B330
4002f
CC