LT1769IFE Linear Technology, LT1769IFE Datasheet - Page 15

• Manufacturer Part Number: LT1769IFE
• Description: IC BATT CHRGR CNSTNT I/V 20TSSOP
• Manufacturer: Linear Technology

Specifications of LT1769IFE

• Function: Charge Management
• Battery Type: Lead Acid, Li-Ion, NiCd, NiMH
• Voltage - Supply: 8 V ~ 25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
Optional Diode Connections
The typical application in Figure 1 shows a single diode
(D3) to isolate the V
block reverse input voltage (both steady state and tran-
sient). This simple connection may be unacceptable in
situations where the system load must be powered from
the battery when the adapter input power is removed. As
shown in Figure 12, a parasitic diode exists from the SW
pin to the V
removed, this diode will become forward biased and will
provide a current path from the battery to the system load.
Because of diode power limitations, it is not recommended
to power the system load through the internal parasitic
diode. To safely power the system load from the battery,
an additional Schottky diode (D4) is needed. For minimum
losses, D4 could be replaced by a low R
which is turned on when the adapter power is removed.
L1
CC
Figure 12. Modified Diode Connection
SW
pin in the LT1769. When the input power is
PARASITIC
INTERNAL
LT1769
DIODE
R
S1
CLP
CLN
V
U
CC
CC
pin from the adaptor input and to
NOTE: CONNECT ALL GND PINS TO EXPANDED PC LANDS FOR PROPER HEAT SINKING
INFORMATION
U
+
+
500
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
C
C1
1 F
R7
IN
W
R
Figure 14. Critical Electrical and Thermal Path Layout
+
S4
D4
D3
DS(ON)
ADAPTER
IN
TO
SYSTEM
LOAD
L1
1769 F12a
U
MOSFET
D1
GND
TO
Layout Considerations
Switch rise and fall times are under 10ns for maximum
efficiency. To minimize radiation, the catch diode, SW pin
and input bypass capacitor leads should be kept as short
as possible. A ground plane should be used under the
switching circuitry to prevent interplane coupling and to
act as a thermal spreading path. All ground pins should be
connected to expanded traces for low thermal resistance.
The fast-switching high current ground path, including the
switch, catch diode and input capacitor, should be kept
very short. Catch diode and input capacitor should be
close to the chip and terminated to the same point. This
path contains nanosecond rise and fall times with several
amps of current. The other paths contain only DC and/or
200kHz tri-wave and are less critical. Figure 13 indicates
the high speed, high current switching path. Figure 14
shows critical path layout. Contact Linear Technology for
the LT1769 circuit PCB layout or Gerber file.
GND
GND
GND
SW
BOOST
UV
GND
GND
OVP
CLP
CLN
COMP1
SENSE
GND
GND
GND
COMP2
UV
PROG
V
V
V
V
SPIN
GND
GND
GND
GND
GND
BAT
IN
OUT
CC1
CC2
CC3
V
C
Figure 13. High Speed Switching Path
C
GND
TO
IN
R
S1
CIRCULATING
C
FREQUENCY
IN
SWITCH NODE
PATH
HIGH
C
OUT
1769 F14
D1
L1
C
OUT
LT1769
BAT
1769 F13
V
15
BAT
1769fa