MAX17041G+T Maxim Integrated Products, MAX17041G+T Datasheet - Page 10

• Manufacturer Part Number: MAX17041G+T
• Description: IC 2-WIRE FG W/MODEL GAUGE
• Manufacturer: Maxim Integrated Products
• Series: ModelGauge™r

Specifications of MAX17041G+T

• Function: Fuel, Gas Gauge/Monitor
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 2.5 V ~ 4.5 V
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-2772G+TRL

Compact, Low-Cost 1S/2S Fuel Gauges
One data bit is transferred during each SCL clock
cycle, with the cycle defined by SCL transitioning low to
high and then high to low. The SDA logic level must
remain stable during the high period of the SCL clock
pulse. Any change in SDA when SCL is high is inter-
preted as a START or STOP control signal.
The bus is defined to be idle, or not busy, when no
master device has control. Both SDA and SCL remain
high when the bus is idle. The STOP condition is the
proper method to return the bus to the idle state.
The master initiates transactions with a START condi-
tion (S) by forcing a high-to-low transition on SDA while
SCL is high. The master terminates a transaction with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high. A Repeated START condition (Sr)
can be used in place of a STOP then START sequence
to terminate one transaction and begin another without
returning the bus to the idle state. In multimaster sys-
tems, a Repeated START allows the master to retain
control of the bus. The START and STOP conditions are
the only bus activities in which the SDA transitions
when SCL is high.
Each byte of a data transfer is acknowledged with an
Acknowledge bit (A) or a No-Acknowledge bit (N). Both
the master and the MAX17040 slave generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep
it low until SCL returns low. To generate a no acknowl-
edge (also called NAK), the receiver releases SDA before
the rising edge of the acknowledge-related clock pulse
and leaves SDA high until SCL returns low. Monitoring the
Acknowledge bits allows for detection of unsuccessful
data transfers. An unsuccessful data transfer can occur if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master should reattempt communication.
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START and STOP Conditions
Acknowledge Bits
Bit Transfer
Bus Idle
A byte of data consists of 8 bits ordered most signifi-
cant bit (MSb) first. The least significant bit (LSb) of
each byte is followed by the Acknowledge bit. The
MAX17040/MAX17041 registers composed of multibyte
values are ordered MSB first. The MSB of multibyte reg-
isters is stored on even data-memory addresses.
A bus master initiates communication with a slave
device by issuing a START condition followed by a
Slave Address (SAddr) and the Read/Write (R/W) bit.
When the bus is idle, the MAX17040/MAX17041 contin-
uously monitor for a START condition followed by its
Slave Address. When the MAX17040/MAX17041
receive a Slave Address that matches the value in the
Slave Address Register, it responds with an
Acknowledge bit during the clock period following the
R/W bit. The 7-bit slave address is fixed to 6Ch (write)/
6DH (read):
The R/W bit following the slave address determines the
data direction of subsequent bytes in the transfer. R/W
= 0 selects a write transaction, with the following bytes
being written by the master to the slave. R/W = 1
selects a read transaction, with the following bytes
being read from the slave by the master.
The MAX17040/MAX17041 are compatible with any bus
timing up to 400kHz. No special configuration is
required to operate at any speed.
The command protocols involve several transaction for-
mats. The simplest format consists of the master writing
the START bit, slave address, R/W bit, and then monitor-
ing the Acknowledge bit for presence of the MAX17040/
MAX17041. More complex formats, such as the Write
Data and Read Data, read data and execute device-spe-
cific operations. All bytes in each command format
require the slave or host to return an Acknowledge bit
before continuing with the next byte. Table 5 shows the
key that applies to the transaction formats.
MAX17040/MAX17041
SLAVE ADDRESS
2-Wire Command Protocols
0110110
Read/Write Bit
Slave Address
Bus Timing
Data Order