MAX17435ETG+T Maxim Integrated Products, MAX17435ETG+T Datasheet - Page 17

IC SMBUS BATT CHARGER 24TQFN

MAX17435ETG+T

Manufacturer Part Number
MAX17435ETG+T
Description
IC SMBUS BATT CHARGER 24TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX17435ETG+T

Function
Charge Management
Battery Type
Multi-Chemistry
Voltage - Supply
8 V ~ 26 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The data (SDA) and clock (SCL) pins have Schmitt-
trigger inputs that can accommodate slow edges.
Choose pullup resistors for SDA and SCL to achieve rise
times according to the SMBus specifications.
Communication starts when the master signals a START
condition, which is a high-to-low transition on SDA, while
SCL is high. When the master has finished communicating,
the master issues a STOP condition, which is a low-to-
high transition on SDA, while SCL is high. The bus is
then free for another transmission. Figures 4 and 5 show
the timing diagrams for signals on the SMBus interface.
Figure 4. SMBus Write Timing
Figure 3. SMBus Write-Word and Read-Word Protocols
SMBCLK
SMBDATA
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
______________________________________________________________________________________
t
SU:STA
S
S
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
a) Write-Word Format
b) Read-Word Format
MSB
MSB
ADDRESS
PRESET TO
0b0001001
ADDRESS
PRESET TO
0b0001001
A
SLAVE
SLAVE
7 bits
7 bits
t
HD:STA
MASTER TO SLAVE
SLAVE TO MASTER
LSB
LSB
t
LOW
W
1b
W
1b
0
0
B
ACK
ACK
t
HIGH
1b
1b
0
0
Relearn() = 0x3D
ChargingCurrent() = 0x14
ChargerVoltage() = 0x15
INP_Voltage() = 0x3E
MSB
MSB
COMMAND
COMMAND
t
SU:DAT
BYTE
BYTE
8 bits
8 bits
C
LSB
LSB
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
t
HD:DAT
D
ACK
ACK
1b
1b
0
0
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
Low-Cost SMBus Chargers
D7
S
MSB
LOW DATA
MSB
BYTE
8 bits
ADDRESS
PRESET TO
E
0b0001001
SLAVE
7 bits
F
LSB
D0
LSB
The address byte, command byte, and data bytes are
transmitted between the START and STOP conditions.
The SDA state is allowed to change only while SCL is
low, except for the START and STOP conditions. Data
is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer
each byte in or out of the MAX17435/MAX17535 because
either the master or the slave acknowledges the receipt
of the correct byte during the ninth clock. The MAX17435/
MAX17535 support the charger commands as described
in Table 4.
ACK
t
HD:DAT
1b
0
1b
R
1
D15
ACK
MSB
HIGH DATA
1b
G
0
BYTE
8 bits
D7
MSB
LOW DATA
LSB
BYTE
D8
8 bits
LSB
ACK P
1b
0
D0
H
High-Frequency,
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
ACK
1b
0
D15
MSB
I
HIGH DATA
BYTE
J
8 bits
LSB
D8
NACK P
K
1b
1
t
SU:STO
L
t
BUF
M
17

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