ADP3820ARTZ-4.2RL7 Analog Devices Inc, ADP3820ARTZ-4.2RL7 Datasheet - Page 6

• Manufacturer Part Number: ADP3820ARTZ-4.2RL7
• Description: IC CHARGER LI-ION 4.2V SOT-23-6
• Manufacturer: Analog Devices Inc
• Type: Battery Chargerr

Specifications of ADP3820ARTZ-4.2RL7

• Function: Charge Management
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 4 V ~ 15 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Output Current: 1mA
• Output Voltage: 4.2V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 15V
• Operating Temp Range: -20C to 85C
• Package Type: SOT-23
• Mounting: Surface Mount
• Pin Count: 6
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP3820ARTZ4.2RCT

ADP3820
APPLICATION INFORMATION
The ADP3820 is very easy to use. A P-channel power MOS-
FET and a small capacitor on the output is all that is needed to
form an inexpensive Li-Ion battery charger. The advantage of
using the ADP3820 controller is that it can directly drive a
PMOS FET to provide a regulated output current until the
battery is charged. When the specified battery voltage is reached,
the charge current is reduced and the ADP3820 maintains the
maximum specified battery voltage accurately.
When fully charged, the circuit in Figure 1 works like a well
known linear regulator, holding the output voltage within the
specified accuracy as needed by single cell Li-Ion batteries. The
output is sensed by the V
battery, the circuit maintains a set charging current determined
by the current sense resistor until the battery is fully charged,
then reduces it to a trickle charge to keep the battery at the
specified voltage. The voltage drop across the R
resistor is sensed by the IS input of the ADP3820. At minimum
battery voltage or at shorted battery, the circuit reduces this
current (foldback) to limit the dissipation of the FET (see Fig-
ure 13). Both the V
to be bypassed by a suitable bypass capacitor.
A 6 V gate-to-source voltage clamp is provided by the ADP3820
to protect the MOSFET gates at higher source voltages. The
ADP3820 also has a TTL SD input, which may be connected to
the input voltage to enable the IC. Pulling it to low or to
ground will disable the FET-drive.
Design Approach
Due to the lower efficiency of Linear Regulator Charging, the
most important factor is the thermal design and cost, which is
the direct function of the input voltage, output current and
thermal impedance between the MOSFET and the ambient
cooling air. The worse-case situation is when the battery is
shorted since the MOSFET has to dissipate the maximum power.
A tradeoff must be made between the charge current, cost and
thermal requirements of the charger. Higher current requires a
larger FET with more effective heat dissipation leading to a
more expensive design. Lowering the charge current reduces
cost by lowering the size of the FET, possibly allowing a smaller
package such as SOT-23-6. The following designs consider both
options. Furthermore, each design is evaluated under two input
source voltage conditions.
Regarding input voltage, there are two options:
A. The input voltage is preregulated, e.g., 5 V
B. The input voltage is not a preregulated source, e.g., a wall
Higher Current Option
A. Preregulated Input Voltage (5 V
For the circuit shown in Figure 1, the required
impedance can be calculated as follows: if the FET data sheet
allows a max FET junction temperature of T
at 50 C ambient and at convection cooling, the maximum al-
lowed T junction temperature rise is thus, T
150 C – 50 C = 100 C.
The maximum current for a shorted or discharged battery is
reduced from the set charge current by a multiplier factor shown
in Figure 13 due to the foldback current limiting feature of the
plug-in transformer with a rectifier and capacitive filter.
IN
input and V
OUT
pin. When charging a discharged
OUT
sense pins of the IC need
10%)
JMAX
JMAX
S
JA
10%
current sense
= 150 C, then
thermal
– T
AMAX
=
–6–
ADP3820. This k factor between V
This thermal impedance can be realized using the transistor
shown in Figure 1 when surface mounted to a 40 40 mm
double-sided PCB with many vias around the tab of the surface-
mounted FET to the backplane of the PCB. Alternatively, a
TO-220 packaged FET mounted to a heatsink could be used.
The
below:
Where the
FET can be read from the FET data sheet. A low cost such
heatsink is type PF430 made by Thermalloy, with a
+25.3 C/W.
The current sense resistor for this application can be simply
calculated:
Where V
voltage at 40 mV–75 mV. For battery charging applications, it
is adequate to use the typical 50 mV midvalue.
B. Nonpreregulated Input Voltage
If the input voltage source is, for example, a rectified and
capacitor-filtered secondary voltage of a small wall plug-in
transformer, the heatsinking requirement is more demanding.
The V
age and full load current. The required thermal impedance can
be calculated the same way as above, but here we have to use
the maximum output rectified voltage, which can be substan-
tially higher than 5 V, depending on transformer regulation and
line voltage variation. For example, if V
The
A low cost heatsink is Type 6030B made by Thermalloy, with a
Lower Current Option
A. Preregulated Input Voltage (5 V
If lower charging current is allowed, the
and the system cost decreased. The lower cost is assured by
using an inexpensive MOSFET with, for example, a NDT452P
in a SOT-23-6 package mounted on a small 40
on double-sided PCB. This provides a convection cooled ther-
mal impedance of
used around the FET to the backplane. Allowing a maximum
FET junction temperature of +150 C, at +50 C ambient, and
at convection cooling the maximum allowed heat rise is thus
150 C–50 C = 100 C.
The maximum foldback current allowed:
Thus the full charging current:
k is calculated in the above example.
k ~ 0.65.
JA
= +12.5 C/W.
= T/(I
JA
INMIN
or thermal impedance of a suitable heatsink is calculated
suitable heatsink thermal impedance:
= T/(I
S
is specified on the data sheet as current limit threshold
I
FB
O
JC
should be specified 5 V, but at the lowest line volt-
, or junction-to-case thermal impedance of the
< (
= T/(
O
k
<
R
JA
k V
S
V
JA
JA
I
= V
–
INMAX
OUTMAX
–
= +55 C/W, presuming many vias are
IN
JC
S
V
JC
/I
) = 100/(1
) = 30.7 – 2 = +28.7 C/W
IN
) = 100/(1
O
= 15.3 – 2 = 13.3 C/W
) = 100/(55
= I
= 0.05/1 = 50 m
FB
/k = 0.5 A
O
of 0 V to about 2.5 V is:
0.65
0.65
10%)
INMAX
JA
value can be increased,
5) = 0.33 A
5) = 30.7 C/W
is 10 V
10) = +15.3 C/W
40 mm area
REV. A
=