IR2177SPBF International Rectifier, IR2177SPBF Datasheet - Page 13

• Manufacturer Part Number: IR2177SPBF
• Description: IC CURRENT SENSE 0.2% 16SOIC
• Manufacturer: International Rectifier

Specifications of IR2177SPBF

• Function: Current Sense
• Accuracy: ±0.2%
• Voltage - Input: 8 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Family Hvic: General Purpose HVICs
• Channels: 1
• Topology: Current Sense
• Application: General Purpose / Motor Control
• Voffset: 600
• Over Current Protection: Yes
• Package: 16 Lead
• Part Status: Active & Preferred
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Sensing Method: -

1.4 Analog Output (OUT)
The analog output is internally buffered and capable
of driving capacitive loads ranging up to 50nF.
V
pin.
Additional circuitry to protect A/D converter input
against excessive voltage is not required.
Hereafter follow some definitions (see Figure 10
and following).
The analog output is also defined by some dynamic
characteristics (see figure 8):
13
2
RH
⋅
f
1
•
•
•
•
•
•
•
•
and V
SYNC
V
Input referred analog offset (V
the input that gives an output that equals
Gain: It is defined by the ratio G
Linearity: It is defined by the maximum
difference between the ideal OUT/V
and the measured curve depurated of the
offset voltage and the gain error.
Slew Rate (SL
OUT measured in V/µs
Settling time (t
analog output (OUT) to reach 90% of final
value.
Measure delay (MD). It is defined by the
time interval between the actual SYNC
edge and PO rising edge.
Step response (SR). Is the time needed by
Output to reach the final value after a step
of the input.
Is always within the following range:
OUT
in
+
RL
=V
MD
set the dynamic range and gain of OUT
inp
=
-V
+
V
inm
t
RH
settl
2
+
≤
OUT
V
settl
SROUT
RL
). The maximum slope of
). Time needed by the
(referred to V
≤
f
SYNC
1
a
=
SS
aos
∆
+
∆
).
OUT
in
MD
): It is
V
curve
in
+
.
t
settl
V
V
V
V
V
V
V
V
V
RH
SS
RL
RH
SS
RH
SS
RL
RL
Figure 12: Linearity error definition
V
Figure 10: Input offset definition
RH
Figure 11: Gain definition
G
G
+V
2
a
a
G
G
RL
id
id
IR2277S/IR2177S(PbF)
V
OUT
OUT
OUT
in
V
aos (V
Linearity
Error
pos
OUT
instead of OUT)
if PO is measured
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V
V
V
in
in
in