MAX6961ATH+ Maxim Integrated Products, MAX6961ATH+ Datasheet - Page 20
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MAX6961ATH+
Manufacturer Part Number
MAX6961ATH+
Description
IC DRVR LED 8X8 44-TQFN
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX6963ATH.pdf
(35 pages)
Specifications of MAX6961ATH+
Display Type
LED
Configuration
8 x 8 (Matrix)
Interface
4-Wire Serial
Digits Or Characters
Any Digit Type
Current - Supply
7.5mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
44-TQFN Exposed Pad
Number Of Segments
64
Low Level Output Current
750000 uA
High Level Output Current
48000 uA
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Supply Current
11 mA
Maximum Power Dissipation
2162 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Table 21. Global Panel Configuration—Color Control (C Data Bit D6) Format
Table 22. Global Panel Configuration—Planes/Intensity Control (PI Data Bit D7) Format
Table 23. Frame Modulation with Pixel Intensity
Table 24. Pixel Intensity Scale Register Format
20
Display panel is built with monocolor or RGB
digits (permanently set this way for MAX6962 and
MAX6963)
Display panel is built with RGY digits
Both
Arithmetic
Geometric
Arithmetic
Geometric
Both
Both
Arithmetic
Geometric
Arithmetic
Geometric
Both
Four display memory planes (0, 1, 2, 3) available;
pixel level-intensity control is 1 bit per pixel per
color (on/off) (permanently set this way for
MAX6961 and MAX6963)
Two display memory planes (0, 1) available;
pixel level-intensity control is 2 bits per pixel per
color (4 levels)
GRADUATION
GRADUATION
______________________________________________________________________________________
PIXEL
PIXEL
REGISTER
REGISTER
1
1
1
0
0
0
1
1
1
0
0
0
PIXEL
PIXEL
DATA
DATA
1
0
0
1
1
0
1
0
0
1
1
0
INTENSITY
INTENSITY
SETTING
SETTING
PIXEL
PIXEL
Full
Full
2/3
1/2
1/3
1/4
Off
2/3
1/2
1/3
1/4
Off
CODE (HEX)
CODE (HEX)
0
0
0
1
1
1
0
0
0
1
1
1
0
0
ADDRESS
ADDRESS
0x0D
0x0D
0x0D
0x0D
1
1
0
0
1
1
0
1
1
0
0
1
1
0
2
1
1
1
0
0
0
2
1
1
1
0
0
0
D7
D7
PI
PI
0
1
PATTERN OF MULTIPLEX CYCLES
PATTERN OF MULTIPLEX CYCLES
FOR WHICH A PIXEL IS ENABLED
FOR WHICH A PIXEL IS ENABLED
3
1
1
0
0
0
0
3
1
1
0
0
0
0
D6
D6
C
C
0
1
4
1
0
1
1
0
0
4
1
0
1
1
0
0
D5
D5
5
1
1
0
0
1
0
5
1
1
0
0
1
0
F
F
F
F
REGISTER DATA
REGISTER DATA
6
1
1
1
0
0
0
6
1
1
1
0
0
0
D4
D4
R
R
R
R
7
1
0
0
1
0
0
7
1
0
0
1
0
0
DP1
DP1
DP1
DP1
D3
D3
8
1
1
1
0
0
0
8
1
1
1
0
0
0
DP0
DP0
DP0
DP0
D2
D2
9
1
1
0
0
1
0
9
1
1
0
0
1
0
D1
D1
IP
IP
IP
IP
10
10
1
0
1
1
0
0
1
0
1
1
0
0
D0
D0
S
S
S
S
11
11
1
1
0
0
0
0
1
1
0
0
0
0