S1D13706F00A200 Epson Electronics America Inc-Semiconductor Div, S1D13706F00A200 Datasheet
S1D13706F00A200
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S1D13706 Embedded Memory LCD Controller Hardware Functional Specification Document Number: X31B-A-001-10 Status: Revision 10.3 Issue Date: 2008/12/16 © SEIKO EPSON CORPORATION 1999-2008. All Rights Reserved. Information in this document is subject to change without notice. You may download and use ...
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Page 2 S1D13706 X31B-A-001-10 Epson Research and Development Revision 10.3 Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...
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Epson Research and Development Vancouver Design Center 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Page 4 6.2.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. ...
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Epson Research and Development Vancouver Design Center 8.3.8 General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Page 6 S1D13706 X31B-A-001-10 Epson Research and Development Revision 10.3 Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...
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Epson Research and Development Vancouver Design Center 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13706 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management ...
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Page 8 2 Features 2.1 Integrated Frame Buffer • Embedded 80K byte SRAM display buffer. 2.2 CPU Interface • Direct support of the following interfaces: Generic MPU bus interface using WAIT# signal. Hitachi SH-3. Hitachi SH-4. Motorola M68K. Motorola MC68EZ328/MC68VZ328 ...
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Epson Research and Development Vancouver Design Center 2.4 Display Modes • 1/2/4/8/16 bit-per-pixel (bpp) color depths. • gray shades using Frame Rate Modulation (FRM) and dithering on mono- chrome passive LCD panels. • 64K colors ...
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Page 10 3 Typical System Implementation Diagrams Generic #1 BUS HIOVDD A[27:17] Decoder CSn# A[16:1] D[15:0] WE0# WE1# RD0# RD1# WAIT# BUSCLK RESET# VSS Figure 3-1: Typical System Diagram (Generic #1 Bus) S1D13706 X31B-A-001-10 . Oscillator BS# M/R# CS# AB[16:1] ...
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Epson Research and Development Vancouver Design Center Generic #2 BUS VDD A[27:17] Decoder CSn# A[16:0] D[15:0] WE# BHE# RD# WAIT# BUSCLK RESET# Figure 3-2: Typical System Diagram (Generic #2 Bus) SH-4 BUS A[25:17] Decoder CSn# A[16:1] D[15:0] WE0# WE1# BS# ...
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Page 12 SH-3 BUS A[25:17] Decoder CSn# A[16:1] D[15:0] WE0# WE1# BS# RD/WR# RD# WAIT# CKIO RESET# VSS Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus) MC68K #1 BUS HIOVDD A[23:17] Decoder FC0, FC1 Decoder A[16:1] D[15:0] LDS# UDS# AS# ...
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Epson Research and Development Vancouver Design Center MC68K #2 BUS A[31:17] Decoder FC0, FC1 Decoder A[16:0] D[31:16] DS# AS# R/W# SIZ1 SIZ0 DSACK1# CLK RESET# Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030) REDCAP2 BUS HIOVDD A[21:17] Decoder ...
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Page 14 MC68EZ328/ MC68VZ328 HIOVDD DragonBall BUS A[25:17] Decoder CSX A[16:1] D[15:0] LWE UWE OE DTACK CLKO RESET VSS Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus) S1D13706 X31B-A-001-10 . Oscillator BS# RD/WR# M/R# CS# AB[16:1] DB[15:0] S1D13706 WE0# ...
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Epson Research and Development Vancouver Design Center 4 Pins 4.1 Pinout Diagram - TQFP15 - 100pin 76 NIOVDD 77 CLKI2 78 CNF7 79 CNF6 80 CNF5 81 CNF4 82 CNF3 83 CNF2 84 CNF1 85 CNF0 86 TESTEN 87 AB16 ...
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Page 16 4.2 Pinout Diagram - Die Form 170 165 175 DIE No. X5534D 180 185 190 195 200 205 210 215 220 225 230 235 Unusable Pad Figure 4-2: Pinout Diagram - Die Form (S1D13706D00A) Chip ...
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Epson Research and Development Vancouver Design Center Table 4-1: Pinout Assignments - Die Form (S1D13706D00A) Pin No. Pad No. Pin Name 1 1 LVDD 2 3 AB3 3 5 AB2 4 8 AB1 5 10 AB0 6 12 CS# 7 ...
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Page 18 4.3 Pin Descriptions Key Input O = Output IO = Bi-Directional (Input/Output Power pin a LIS = LVTTL Schmitt input LI = LVTTL input LB2A = LVTTL IO buffer (6mA/-6mA@3.3V) LB3P = Low noise ...
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Epson Research and Development Vancouver Design Center Pin Name Type Pin # Cell 18-24, DB[15:0] IO LB2A 27-35 WE0 LIS WE1 LIS CS M/ LIS Hardware Functional Specification Issue Date: 2008/12/16 ...
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Page 20 Pin Name Type Pin # Cell BS LIS RD/WR LIS RD LIS S1D13706 X31B-A-001-10 Table 4-2: Host Interface Pin Descriptions IO RESET# Voltage State This input pin has multiple functions. • For ...
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Epson Research and Development Vancouver Design Center Pin Name Type Pin # Cell WAIT LB2A RESET LIS Hardware Functional Specification Issue Date: 2008/12/16 Table 4-2: Host Interface Pin Descriptions IO RESET# Voltage State During a data ...
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Page 22 4.3.2 LCD Interface Pin Name Type Pin # Cell 74-64, FPDAT[17:0] O LB3P 61-55 FPFRAME O 52 LB3P FPLINE O 53 LB3P FPSHIFT O 54 LB3P DRDY O 48 LO3 GPIO0 IO 45 LB3M GPIO1 IO 44 LB3M ...
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Epson Research and Development Vancouver Design Center Pin Name Type Pin # Cell GPIO2 IO 43 LB3M GPIO3 IO 42 LB3M GPIO4 IO 41 LB3M GPIO5 IO 40 LB3M GPIO6 IO 39 LB3M PWMOUT O 38 LB3P CVOUT O 46 ...
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Page 24 4.3.3 Clock Input Pin Name Type Pin # Cell CLKI CLKI2 4.3.4 Miscellaneous Pin Name Type Pin # Cell CNF[7:0] I 78-85 LI GPO O 47 LO3 TESTEN 4.3.5 ...
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Epson Research and Development Vancouver Design Center 4.4 Summary of Configuration Options These pins are used for configuration of the S1D13706 and must be connected directly to NIOV state at any other time has no effect. Table ...
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Page 26 4.5 Host Bus Interface Pin Mapping S1D13706 Generic #1 Generic #2 Pin Name AB[16:1] A[16:1] A[16:1] 1 AB0 A0 DB[15:0] D[15:0] D[15:0] CS# External Decode M/R# CLKI BUSCLK BUSCLK BS# Connected to V Connected to RD/WR# RD1# RD# ...
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Epson Research and Development Vancouver Design Center 4.6 LCD Interface Pin Mapping Monochrome Passive Panel Pin Name Single 4-bit 4-bit 8-bit FPFRAME FPLINE FPSHIFT DRDY MOD FPDAT0 driven 0 D0 driven 0 FPDAT1 driven 0 D1 driven 0 FPDAT2 driven ...
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Page 28 5 D.C. Characteristics Symbol Parameter Core V Supply Voltage Supply Voltage DD V Input Voltage IN V Output Voltage OUT T Storage Temperature STG T Solder Temperature/Time SOL Table 5-2: Recommended Operating Conditions Symbol Parameter ...
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Epson Research and Development Vancouver Design Center 6 A.C. Characteristics Conditions: 6.1 Clock Timing 6.1.1 Input Clocks Clock Input Waveform 90 10 Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide ...
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Page 30 Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 Symbol f Input Clock Frequency (CLKI) OSC T Input Clock period (CLKI) OSC t Input Clock Pulse Width High (CLKI) PWH t Input Clock ...
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Epson Research and Development Vancouver Design Center 6.1.2 Internal Clocks Symbol Parameter f Bus Clock frequency BCLK f Memory Clock frequency MCLK f Pixel Clock frequency PCLK f PWM Clock frequency PWMCLK Note For further information on internal clocks, refer ...
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Page 32 6.2 CPU Interface Timing The following section includes CPU interface AC Timing for both 2.0V and 3.3V. The 2.0V timings are based on HIO V HIO V DD 6.2.1 Generic #1 Interface Timing T CLK CLK t3 A[16:1] ...
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Epson Research and Development Vancouver Design Center Symbol Parameter f Bus Clock frequency CLK T Bus Clock period CLK t1 Clock pulse width high t2 Clock pulse width low A[16:1], M/R# setup to first CLK rising edge where CS# = ...
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Page 34 6.2.2 Generic #2 Interface Timing (e.g. ISA) T BUSCLK BUSCLK t3 SA[16:0] M/R#, SBHE# CS# MEMR# MEMW# IOCHRDY SD[15:0] (write) SD[15:0] (read) S1D13706 X31B-A-001- t11 t13 Figure 6-3: Generic #2 Interface Timing ...
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Epson Research and Development Vancouver Design Center Symbol Parameter f Bus Clock frequency BUSCLK T Bus Clock period BUSCLK t1 Clock pulse width high t2 Clock pulse width low SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge t3 where ...
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Page 36 6.2.3 Hitachi SH-4 Interface Timing T t1 CKIO CKIO t3 A[16:1], M/R# RD/WR# t5 BS# t7 CSn# WEn# RD# Hi-Z RDY# D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) S1D13706 X31B-A-001- t10 t11 t15 Figure 6-4: Hitachi ...
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Epson Research and Development Vancouver Design Center Symbol Parameter f Clock frequency CKIO T Clock period CKIO t1 Clock pulse width low t2 Clock pulse width high t3 A[16:1], M/R#, RD/WR# setup to CKIO t4 A[16:1], M/R#, RD/WR# hold from ...
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Page 38 6.2.4 Hitachi SH-3 Interface Timing T t1 CKIO CKIO t3 A[16:1], M/R# RD/WR# t5 BS# t7 CSn# WEn# RD# t12 Hi-Z WAIT# D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) S1D13706 X31B-A-001- t10 t14 Figure 6-5: Hitachi ...
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Epson Research and Development Vancouver Design Center Symbol Parameter f Bus Clock frequency CKIO T Bus Clock period CKIO t1 Bus Clock pulse width low t2 Bus Clock pulse width high t3 A[16:1], M/R#, RD/WR# setup to CKIO t4 CSn# ...
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Page 40 6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) T CLK t1 CLK A[16:1] M/R# CS# AS# UDS# LDS# R/W# t15 DTACK# D[15:0](write) D[15:0](read) Figure 6-6: Motorola MC68K #1 Interface Timing S1D13706 X31B-A-001- t10 ...
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Epson Research and Development Vancouver Design Center Table 6-9: Motorola MC68K #1 Interface Timing Symbol Parameter f Bus Clock Frequency CLK T Bus Clock period CLK t1 Clock pulse width high t2 Clock pulse width low A[16:1], M/R# setup to ...
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Page 42 6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) T CLK CLK A[16:0] M/R#, SIZ[1:0] CS# AS# DS# t13 R/W# t15 DSACK1# D[31:16](write) D[31:16](read) Figure 6-7: Motorola MC68K #2 Interface Timing Note For information on the implementation of the ...
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Epson Research and Development Vancouver Design Center Table 6-10: Motorola MC68K #2 Interface Timing Symbol Parameter f Bus Clock frequency CLK T Bus Clock period CLK t1 Clock pulse width high t2 Clock pulse width low A[16:0], SIZ[1:0], M/R# setup ...
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Page 44 6.2.7 Motorola REDCAP2 Interface Timing T t1 CKO CKO M/R# A[16:1] R/W CSn EB0 EB1 (write) D[15:0] Hi-Z (write) OE EB0 EB1 (read) D[15:0] Hi-Z (read) Note: CSn may be any of CS0 - CS4. Figure 6-8: Motorola ...
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Epson Research and Development Vancouver Design Center Table 6-11: Motorola REDCAP2 Interface Timing Symbol Parameter f Bus Clock frequency CKO T Bus Clock period CKO t1 Bus Clock pulse width low t2 Bus Clock pulse width high t3 A[16:1], M/R#, ...
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Page 46 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) T CLKO CLKO t3 A[16:1] t6 CSX t8 UWE/LWE (write) OE (read) D[15:0] Hi-Z (write) Hi-Z D[15:0] (read) t16 DTACK Figure 6-9: Motorola DragonBall Interface with DTACK Timing S1D13706 ...
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Epson Research and Development Vancouver Design Center Table 6-12: Motorola DragonBall Interface with DTACK Timing Symbol Parameter f Bus Clock frequency CLKO T Bus Clock period CLKO t1 Clock pulse width high t2 Clock pulse width low A[16:1] setup 1st ...
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Page 48 6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) T CLKO CLKO t3 A[16:1] t6 CSX t8 UWE/LWE (write) OE (read) D[15:0] Hi-Z (write) Hi-Z D[15:0] (read) Figure 6-10: Motorola DragonBall Interface without DTACK# Timing S1D13706 X31B-A-001-10 t1 ...
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Epson Research and Development Vancouver Design Center Table 6-13: Motorola DragonBall Interface without DTACK Timing Symbol Parameter f Bus Clock frequency CLKO T Bus Clock period CLKO t1 Clock pulse width high t2 Clock pulse width low A[16:1] setup 1st ...
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Page 50 6.3 LCD Power Sequencing 6.3.1 Passive/TFT Power-On Sequence GPO* Power Save Mode Enable** (REG[A0h] bit 0) LCD Signals*** *It is recommended to use the general purpose output pin GPO to control the LCD bias power. **The LCD power-on ...
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Epson Research and Development Vancouver Design Center 6.3.2 Passive/TFT Power-Off Sequence GPO* Power Save Mode Enable** (REG[A0h] bit 0) LCD Signals*** *It is recommended to use the general purpose output pin GPO to control the LCD bias power. **The LCD ...
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Page 52 6.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section. VPS VDPS VPW VT Table 6-16: Panel ...
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Epson Research and Development Vancouver Design Center 6.4.1 Generic STN Panel Timing VPW FPFRAME FPLINE 1 MOD (DRDY) FPDAT[17:0] FPLINE FPSHIFT 1PCLK 2 MOD (DRDY) HDPS FPDAT[17:0] Hardware Functional Specification Issue Date: 2008/12/ Frame) VDP HT (= ...
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Page Vertical Total = [(REG[19h] bits 1-0, REG[18h] bits 7- lines VPS = FPFRAME Pulse Start Position = 0 lines, because (REG[27h] bits 1-0, REG[26h] bits 7- VPW = FPFRAME Pulse Width = ...
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Epson Research and Development Vancouver Design Center 6.4.2 Single Monochrome 4-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid FPLINE DRDY (MOD) FPSHIFT FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid * Diagram drawn with 2 FPLINE vertical blank period ...
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Page 56 Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE falling edge t2 FPFRAME hold ...
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Epson Research and Development Vancouver Design Center 6.4.3 Single Monochrome 8-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid FPLINE DRDY (MOD) FPSHIFT FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid * ...
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Page 58 Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE falling edge t2 FPFRAME hold ...
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Epson Research and Development Vancouver Design Center 6.4.4 Single Color 4-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid FPLINE DRDY (MOD) .5Ts FPSHIFT Invalid 1-R1 FPDAT7 Invalid FPDAT6 Invalid 1-B1 FPDAT5 Invalid 1-R2 FPDAT4 Notes: - FPSHIFT uses extended ...
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Page 60 Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4] Figure 6-20: Single Color 4-Bit Panel A.C. Timing Table 6-19: Single Color 4-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE falling edge t2 FPFRAME hold ...
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Epson Research and Development Vancouver Design Center 6.4.5 Single Color 8-Bit Panel Timing (Format 1) FPFRAME FPLINE FPDAT[7:0] Invalid FPLINE 2Ts FPSHIFT FPSHIFT2 FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid Notes: ...
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Page 62 Sync Timing FPFRAME FPLINE Data Timing FPLINE FPSHIFT FPSHIFT2 FPDAT[7:0] Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol t1 FPFRAME setup to FPLINE falling edge ...
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Epson Research and Development Vancouver Design Center 6.4.6 Single Color 8-Bit Panel Timing (Format 2) FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid FPLINE DRDY (MOD) 2Ts FPSHIFT Ts FPDAT7 Invalid 1-R1 FPDAT6 Invalid 1-G1 FPDAT5 Invalid 1-B1 FPDAT4 Invalid 1-R2 FPDAT3 ...
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Page 64 Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0] Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2) Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol t1 FPFRAME setup to FPLINE falling ...
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Epson Research and Development Vancouver Design Center 6.4.7 Single Color 16-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] Invalid FPLINE DRDY (MOD) 3Ts FPSHIFT Invalid 1-R1 - FPDAT15 Invalid 1-B1 FPDAT14 Invalid FPDAT13 1-G2 Invalid FPDAT12 1-R3 FPDAT7 Invalid 1-B3 ...
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Page 66 Sync Timing FPFRAME FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0] Figure 6-26: Single Color 16-Bit Panel A.C. Timing Table 6-22: Single Color 16-Bit Panel A.C. Timing Symbol t1 FPFRAME setup to FPLINE falling edge t2 FPFRAME hold ...
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Epson Research and Development Vancouver Design Center 6.4.8 Generic TFT Panel Timing VPS FPFRAME FPLINE DRDY FPDAT[17:0] HPS HPW FPLINE FPSHIFT DRDY HDPS FPDAT[17:0] invalid VT = Vertical Total VPS = FPFRAME Pulse Start Position VPW = FPFRAME Pulse Width ...
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Page 68 6.4.9 9/12/18-Bit TFT Panel Timing FPFRAME FPLINE FPDAT[17:0] LINE240 DRDY FPLINE FPSHIFT DRDY FPDAT[17:0] Note: DRDY is used to indicate the first pixel Example Timing for 18-bit 320x240 panel VDP = Vertical Display Period = VDP Lines VNDP ...
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Epson Research and Development Vancouver Design Center FPFRAME t3 FPLINE FPLINE DRDY t9 t10 t11 FPSHIFT FPDAT[17:0] Note: DRDY is used to indicate the first pixel Hardware Functional Specification Issue Date: 2008/12/ t12 invalid Figure 6-29: TFT ...
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Page 70 Symbol FPFRAME cycle time t1 FPFRAME pulse width low t2 FPFRAME falling edge to FPLINE falling edge phase difference t3 FPLINE cycle time t4 FPLINE pulse width low t5 FPLINE Falling edge to DRDY active t6 DRDY pulse ...
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Epson Research and Development Vancouver Design Center 6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) t12 GPIO0 (PS) t13 GPIO2 (REV) Figure 6-30: 160x160 Sharp ‘Direct’ ...
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Page 72 Table 6-24: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing Symbol FPLINE start position t1 Horizontal total period t2 FPLINE width t3 FPSHIFT period t4 t5 Data setup to FPSHIFT rising edge t6 Data hold from FPSHIFT rising edge Horizontal ...
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Epson Research and Development Vancouver Design Center FPDAT[17:0] t4 FPFRAME (SPS) t5 GPIO1 (CLS) GPIO0 (PS) FPLINE (LP) FPSHIFT (CLK) GPIO1 (CLS) GPIO0 (PS) Figure 6-31: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing Hardware Functional Specification Issue Date: 2008/12/16 t1 ...
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Page 74 Table 6-25: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing Symbol Vertical total period t1 Vertical display start position t2 Vertical display period t3 Vertical sync pulse width t4 FPFRAME falling edge to GPIO1 alternate timing start t5 GPIO1 ...
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Epson Research and Development Vancouver Design Center 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) t12 GPIO0 (PS) t13 GPIO2 (REV) Figure 6-32: 320x240 Sharp ‘Direct’ ...
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Page 76 Table 6-26: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing Symbol FPLINE start position t1 Horizontal total period t2 FPLINE width t3 FPSHIFT period t4 t5 Data setup to FPSHIFT rising edge t6 Data hold from FPSHIFT rising edge ...
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Epson Research and Development Vancouver Design Center 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) t1 FPLINE (LP) t2 FPSHIFT (XSCL) t4 FPDAT[17:0] (R,G,B) t7 t10 GPIO4 (RES) t11 GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 ...
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Page 78 Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing Symbol FPLINE pulse width t1 FPLINE falling edge to FPSHIFT start position t2 FPSHIFT active period t3 FPSHIFT start to first data t4 Horizontal display period t5 t6 Last data ...
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Epson Research and Development Vancouver Design Center FPFRAME (DY) GPIO1 (YSCL) GPIO0 (XINH) FPDAT[17:0] (R,G,B) GPIO2 (FR) (odd frame) GPIO2 (FR) (even frame) Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing Symbol ...
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Page 80 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) t1 FPLINE (LP) t2 FPSHIFT (XSCL) FPDAT[17:0] (R,G,B) t7 t10 GPIO4 (RES) GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1) Figure 6-37: 320x240 Epson D-TFD Panel ...
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Epson Research and Development Vancouver Design Center Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing Symbol FPLINE pulse width t1 FPLINE falling edge to FPSHIFT start position t2 FPSHIFT active period t3 FPSHIFT start to first data t4 Horizontal display ...
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Page 82 GPIO4 (RES) t2 DRDY (GCP) GCP Data Register 1 1 (REG[2Ch]) bit7 Figure 6-38: 320x240 Epson D-TFD Panel GCP Horizontal Timing Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing Symbol Half of the horizontal total period t1 ...
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Epson Research and Development Vancouver Design Center FPFRAME (DY) GPIO1 (YSCL) GPIO0 (XINH) FPDAT[17:0] (R,G,B) GPIO2 (FR) (odd frame) GPIO2 (FR) (even frame) Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing Symbol ...
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Page 84 7 Clocks 7.1 Clock Descriptions 7.1.1 BCLK BCLK is an internal clock derived from CLKI. BCLK can be a divided version (÷1, ÷2, ÷3, ÷4) of CLKI. CLKI is typically derived from the host CPU bus clock. The ...
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Epson Research and Development Vancouver Design Center 7.1.3 PCLK PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match the optimum frame rate of the LCD panel. See Section 9, “Frame Rate Calculation” ...
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Page 86 There is a relationship between the frequency of MCLK and PCLK that must be maintained. SwivelView Orientation SwivelView 0° and 180° SwivelView 90° and 270° 7.1.4 PWMCLK PWMCLK is the internal clock used by the Pulse Width Modulator ...
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Epson Research and Development Vancouver Design Center 7.2 Clock Selection The following diagram provides a logical representation of the S1D13706 internal clocks. CLKI CLKI2 Note 1 CNF[7:6] must be set at RESET#. Hardware Functional Specification Issue Date: 2008/12/16 00 ÷2 ...
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Page 88 7.3 Clocks versus Functions Table 7-6: “S1D13706 Internal Clock Requirements”, lists the internal clocks required for the following S1D13706 functions. Table 7-6: S1D13706 Internal Clock Requirements Function Register Read/Write Memory Read/Write Look-Up Table Register Read/Write Software Power Save ...
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Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13706 registers. It also provides detailed information about the layout and usage of each register. 8.1 Register Mapping The S1D13706 registers are ...
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Page 90 Register + REG[7Ch] PIP Window Display Start Address Register 0 + REG[7Eh] PIP Window Display Start Address Register 2 + REG[81h] PIP Window Line Address Offset Register 1 + REG[85h] PIP Window X Start Position Register 1 + ...
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Epson Research and Development Vancouver Design Center 8.3 Register Descriptions Unless specified otherwise, all register bits are set to 0 during power-on. 8.3.1 Read-Only Configuration Registers Revision Code Register REG[00h] Product Code Bits 5 Note The S1D13706 returns ...
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Page 92 8.3.2 Clock Configuration Registers Memory Clock Configuration Register REG[04h] n/a MCLK Divide Select Bits 1 bits 5-4 MCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Memory Clock (MCLK) from the ...
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Epson Research and Development Vancouver Design Center Pixel Clock Configuration Register REG[05h] n/a PCLK Divide Select Bits 2 bits 6-4 PCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Pixel Clock (PCLK) from ...
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Page 94 8.3.3 Look-Up Table Registers Note The S1D13706 has three 256-position, 6-bit wide LUTs, one for each of red, green, and blue (see Section 11, “Look-Up Table Architecture” on page 129). Look-Up Table Blue Write Data Register REG[08h] LUT ...
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Epson Research and Development Vancouver Design Center Look-Up Table Red Write Data Register REG[0Ah] LUT Red Write Data Bits 5 bits 7-2 LUT Red Write Data Bits [5:0] This register contains the data to be written to the ...
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Page 96 Look-Up Table Green Read Data Register REG[0Dh] LUT Green Read Data Bits 5 bits 7-2 LUT Green Read Data Bits [5:0] This register contains the data from the green component of the Look-Up Table. The LUT ...
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Epson Research and Development Vancouver Design Center 8.3.4 Panel Configuration Registers Panel Type Register REG[10h] Panel Data Color/Mono. Panel Data Width Bits 1-0 Format Select Panel Select 7 6 bit 7 Panel Data Format Select When this bit = 0, ...
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Page 98 bits 1-0 Panel Type Bits[1:0] These bits select the panel type. REG[10h] Bits[1:0] MOD Rate Register REG[11h] n bits 5-0 MOD Rate Bits [5:0] These bits are for passive LCD panels only. When these bits are ...
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Epson Research and Development Vancouver Design Center Horizontal Display Period Register REG[14h] n bits 6-0 Horizontal Display Period Bits [6:0] These bits specify the LCD panel Horizontal Display Period (HDP pixel resolution. The Horizontal Display Period ...
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Page 100 Vertical Total Register 0 REG[18h Vertical Total Register 1 REG[19h bits 9-0 Vertical Total Bits [9:0] These bits specify the LCD panel Vertical Total period line resolution. The Vertical Total is the ...
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Epson Research and Development Vancouver Design Center Vertical Display Period Start Position Register 0 REG[1Eh Vertical Display Period Start Position Register 1 REG[1Fh bits 9-0 Vertical Display Period Start Position Bits [9:0] These bits specify the ...
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Page 102 FPLINE Pulse Start Position Register 0 REG[22h FPLINE Pulse Start Position Register 1 REG[23h bits 9-0 FPLINE Pulse Start Position Bits [9:0] These bits specify the start position of the horizontal sync signal, in ...
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Epson Research and Development Vancouver Design Center FPFRAME Pulse Start Position Register 0 REG[26h FPFRAME Pulse Start Position Register 1 REG[27h bits 9-0 FPFRAME Pulse Start Position Bits [9:0] These bits specify the start position of ...
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Page 104 D-TFD GCP Data Register REG[2Ch bits 7-0 D-TFD GCP Data Bits [7:0] For D-TFD panel only. This register stores the data to be written to the GCP data bits and is controlled by the D-TFD GCP ...
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Epson Research and Development Vancouver Design Center 8.3.5 Display Mode Registers Display Mode Register REG[70h] Hardware Dithering Display Blank Video Invert Disable Enable 7 6 bit 7 Display Blank When this bit = 0, the LCD display pipeline is enabled. ...
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Page 106 bit 5 Hardware Video Invert Enable This bit allows the Video Invert feature to be controlled using the General Purpose IO pin GPIO0. This option is not available if configured for a HR-TFT or D-TFD as GPIO0 is ...
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Epson Research and Development Vancouver Design Center bits 2-0 Bit-per-pixel Select Bits [2:0] These bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the PIP Note and 8 bpp color ...
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Page 108 bit 6 Display Data Byte Swap The display pipe fetches 32-bits of data from the display buffer. This bit enables byte 0 and byte swapped, and byte 2 and byte swapped, before ...
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Epson Research and Development Vancouver Design Center Main Window Display Start Address Register 0 REG[74h Main Window Display Start Address Register 1 REG[75h Main Window Display Start Address Register 2 REG[76h bits 16-0 Main ...
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Page 110 Main Window Line Address Offset Register 0 REG[78h Main Window Line Address Offset Register 1 REG[79h bits 9-0 Main Window Line Address Offset Bits [9:0] This register specifies the offset, in DWORDS, from the ...
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Epson Research and Development Vancouver Design Center 8.3.6 Picture-in-Picture Plus (PIP + PIP Window Display Start Address Register 0 REG[7C PIP Window Display Start Address Register 1 REG[7Dh PIP Window Display Start Address Register ...
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Page 112 + PIP Window Line Address Offset Register 0 REG[80h PIP Window Line Address Offset Register 1 REG[81h bits 9-0 PIP Window Line Address Offset Bits [9:0] These bits are the LCD display’s ...
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Epson Research and Development Vancouver Design Center + PIP Window X Start Position Register 0 REG[84h PIP Window X Start Position Register 1 REG[85h bits 9-0 PIP Window X Start Position Bits [9:0] These ...
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Page 114 + PIP Window Y Start Position Register 0 REG[88h PIP Window Y Start Position Register 1 REG[89h bits 9-0 PIP Window Y Start Position Bits [9:0] These bits determine the Y start ...
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Epson Research and Development Vancouver Design Center + PIP Window X End Position Register 0 REG[8Ch PIP Window X End Position Register 1 REG[8Dh bits 9-0 PIP Window X End Position Bits [9:0] These ...
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Page 116 + PIP Window Y End Position Register 0 REG[90h PIP Window Y End Position Register 1 REG[91h bits 9-0 PIP Window Y End Position Bits [9:0] These bits determine the Y end ...
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Epson Research and Development Vancouver Design Center 8.3.7 Miscellaneous Registers Power Save Configuration Register REG[A0h] Vertical Non- Display Period Status (RO bit 7 Vertical Non-Display Period Status This is a read-only status bit. When this bit = 0, ...
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Page 118 Reserved REG[A2h] Reserved 7 6 bit 7 Reserved. This bit must remain at 0. bit 0 Reserved. This bit must remain at 0. Reserved REG[A3h] Reserved 7 6 bit 7 Reserved. This bit must remain at 0. Scratch ...
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Epson Research and Development Vancouver Design Center 8.3.8 General IO Pins Registers General Purpose IO Pins Configuration Register 0 REG[A8h] GPIO6 Pin IO GPIO5 Pin IO n/a Configuration Configuration 7 6 Note 1 If CNF3 = 0 at RESET#, then ...
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Page 120 General Purpose IO Pins Status/Control Register 0 REG[ACh] GPIO6 Pin IO GPIO5 Pin IO n/a Status Status 7 6 Note For information on GPIO pin mapping when HR-TFT/D-TFD panels are selected, see Table 4-9: “LCD Interface Pin Mapping,” ...
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Epson Research and Development Vancouver Design Center bit 3 GPIO3 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is configured as an output, writing this bit drives ...
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Page 122 bit 0 GPIO0 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is configured as an output, writing this bit drives GPIO0 high and writing a ...
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Epson Research and Development Vancouver Design Center 8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers PWM Clock Divider PWMCLK Clock Source / PWM Clock Divide Select value CV Pulse Divider Clock Source ...
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Page 124 bit 3 and bit 0 CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0) These bits control the CVOUT pin and CV Pulse circuitry as follows. Bit don’t care ...
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Epson Research and Development Vancouver Design Center PWM Clock / CV Pulse Configuration Register REG[B1h] PWM Clock Divide Select Bits 3 bits 7-4 PWM Clock Divide Select Bits [3:0] The value of these bits represents the power of ...
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Page 126 CV Pulse Burst Length Register REG[B2h bits 7-0 CV Pulse Burst Length Bits [7:0] The value of this register determines the number of pulses generated in a single CV Pulse burst: Number of pulses in a ...
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Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation The following formula is used to calculate the display frame rate. Where: f PCLK HT VT Hardware Functional Specification Issue Date: 2008/12/16 f PCLK FrameRate = ------------------------------- - ( ...
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Page 128 10 Display Data Formats The following diagrams show the display mode data formats for a little-endian system. 1 bpp: bit Byte Byte Byte 2 16 Host Address ...
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Epson Research and Development Vancouver Design Center 11 Look-Up Table Architecture The following figures are intended to show the display data output path only. Note When Video Data Invert is enabled the video data is inverted after the Look-Up Table. ...
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Page 130 4 Bit-per-pixel Monochrome Mode Green Look-Up Table 256x6 bit-per-pixel data from Display Buffer Figure 11-3: 4 Bit-per-pixel ...
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Epson Research and Development Vancouver Design Center 16 Bit-Per-Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth– See “Display Data Formats” on page 128.. 11.2 Color Modes 1 Bit-Per-Pixel Color Red ...
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Page 132 2 Bit-Per-Pixel Color Red Look-Up Table 256x6 Green Look-Up Table 256x6 Blue Look-Up Table 256x6 ...
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Epson Research and Development Vancouver Design Center 4 Bit-Per-Pixel Color Red Look-Up Table 256x6 Green Look-Up Table 256x6 00 01 ...
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Page 134 8 Bit-per-pixel Color Mode Red Look-Up Table 256x6 Green Look-Up Table 256x6 ...
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Epson Research and Development Vancouver Design Center 12 SwivelView™ 12.1 Concept Most computer displays are refreshed in landscape orientation – from left to right and top to bottom. Computer images are stored in the same manner. SwivelView™ is designed to ...
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Page 136 12.2.1 Register Programming 90° SwivelView™ Mode Enable Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 01. Display Start Address The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start Address registers (REG[74h], REG[75h], ...
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Epson Research and Development Vancouver Design Center 12.3 180° SwivelView™ The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13706 in the following ...
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Page 138 Line Address Offset The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the display width and programmed using the following formula. Main Window Line Address Offset bits 9:0 12.4 270° SwivelView™ 270° SwivelView™ requires the ...
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Epson Research and Development Vancouver Design Center 12.4.1 Register Programming 270° SwivelView™ Mode Enable Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 11. The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address registers ...
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Page 140 13 Picture-in-Picture Plus (PIP 13.1 Concept Picture-in-Picture Plus enables a secondary window (or PIP display window. The PIP and is controlled through the PIP REG[91h]). The PIP the main window. The following diagram shows an example of a ...
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Epson Research and Development Vancouver Design Center 13.2 With SwivelView Enabled 13.2.1 SwivelView 90° TM 90° SwivelView + PIP window x end position (REG[8Dh],REG[8Ch]) Figure 13-2: Picture-in-Picture Plus with SwivelView 90° enabled 13.2.2 SwivelView 180° TM 180° SwivelView PIP + ...
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Page 142 13.2.3 SwivelView 270° TM 270° SwivelView + PIP window y end position (REG[91h],REG[90h]) + PIP window y start position (REG[89h],REG[88h]) + PIP window x start position (REG[85h],REG[84h]) panel’s origin Figure 13-4: Picture-in-Picture Plus with SwivelView 270° enabled S1D13706 ...
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Epson Research and Development Vancouver Design Center 14 Big-Endian Bus Interface 14.1 Byte Swapping Bus Data The display buffer and register architecture of the S1D13706 is inherently little-endian host bus interface is configured as big-endian (CNF4 = 1 ...
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Page 144 14.1.1 16 Bpp Color Depth For 16 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set System Memory Address MSB LSB System ...
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Epson Research and Development Vancouver Design Center 14.1.2 1/2/4/8 Bpp Color Depth For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the display data. For 1/2/4/8 bpp color depth, the Display Data Byte ...
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Page 146 15 Power Save Mode A software initiated Power Save Mode is incorporated into the S1D13706 to accommodate the need for power reduction in the hand-held devices market. This mode is enabled via the Power Save Mode Enable bit ...
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Epson Research and Development Vancouver Design Center 16 Mechanical Data 100-pin TQFP15 surface mount package 76 100 All dimensions in mm Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A) Hardware Functional Specification Issue Date: 2008/12/16 ± 0.4 16.0 ± 0.1 14.0 ...
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Page 148 17 References The following documents contain additional information related to the S1D13706. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • 13706CFG ...
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Epson Research and Development Vancouver Design Center 18 Sales and Technical Support AMERICA EPSON ELECTRONICS AMERICA, INC. 2580 Orchard Parkway San Jose , CA 95131,USA Phone: +1-800-228-3964 FAX: +1-408-922-0238 EUROPE EPSON EUROPE ELECTRONICS GmbH Riesstrasse 15, 80992 Munich, GERMANY Phone: ...
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Page 150 X31A-A-001-10 Revision 10.3 - Issued: December 16, 2008 • all changes from the previous revision are in Red • section 19 - updated Sales and Technical Support addresses X31A-A-001-10 Revision 10.2 - Issued: February 13, 2008 • all ...