LTC4252-1IMS8#TR Linear Technology, LTC4252-1IMS8#TR Datasheet - Page 23

• Manufacturer Part Number: LTC4252-1IMS8#TR
• Description: IC CNTRLR HOTSWAP NEGVOLT 8-MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252-1IMS8#TR

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252-1
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC4252-1IMS8TR; LTC42521IMS8TR

APPLICATIO S I FOR ATIO
a GATE start-up cycle begins. SS ramps up as dictated by
R
amplifier until SS crosses 20 • V
58µA sources into the external MOSFET gate and compen-
sation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
V
current. If the SENSE voltage (V
ACL
SS
• C
(t) and soft-start limits the slew rate of the load
(–48RTN) – (–48V)
SS
GND – V
; GATE is held low by the analog current limit
PWRGD
TIMER
SENSE
DRAIN
UV/OV
EE
GATE
V
OUT
V
OR
SS
IN
U
1
Figure 10. Power-Up Timing with a Short Pin (All Waveforms are Referenced to V
V
GATEL
V
U
UVHI
V
LKO
UV CLEARS V
2
OS
SENSE
. Upon releasing GATE,
W
UVHI
– V
5.8µA
, CHECK OV < V
INITIAL TIMING
EE
) reaches the
U
20 • (V
20 • (V
OVHI
V
ACL
TMRH
, GATE < V
CB
20 • V
V
+ V
+ V
TMRL
OS
OS
OS
)
)
58µA
GATEL
3 4 56
V
activates. The TIMER capacitor, C
+ 8 • I
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below V
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V
5.8µA discharge cycle (cool off). When GATE ramps past
V
time point 11, GATE reaches its maximum voltage as
determined by V
TIMER CLEARS V
CB
GATEH
230µA + 8 • I
, SENSE < V
threshold at time point 7, the circuit breaker TIMER
START-UP
DRN
LTC4252A-1/LTC4252A-2
GATE
7
58µA
threshold at time point 10, PWRGD pulls low. At
CB
) current pull-up. As the load capacitor nears full
8 9
CB
DRN
and the fault TIMER cycle ends, followed by a
TMRL
1011
, SS < 20 • V
LTC4252-1/LTC4252-2
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
IN
– V
.
GATEH
OS
5.8µA
AND TIMER < V
GATEL
, SENSE < V
TMRL
T
EE
, is charged by a (230µA
)
5.8µA
CB
4252-1/2 F10
AND SS < 20 • V
23
OS
ACL
425212fb
(t).