LTC4252A-2CMS#TR Linear Technology, LTC4252A-2CMS#TR Datasheet - Page 29

IC CTRLR HOTSWAP NEG VOLT 10MSOP

LTC4252A-2CMS#TR

Manufacturer Part Number
LTC4252A-2CMS#TR
Description
IC CTRLR HOTSWAP NEG VOLT 10MSOP
Manufacturer
Linear Technology
Type
Hot-Swap Controllerr
Datasheets

Specifications of LTC4252A-2CMS#TR

Applications
General Purpose
Internal Switch(s)
No
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
Family Name
LTC4252A-2
Package Type
MSOP
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Product Depth (mm)
3mm
Product Height (mm)
0.86mm
Product Length (mm)
3mm
Mounting
Surface Mount
Pin Count
10
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC4252A-2CMS#TRLTC4252A-2CMS
Manufacturer:
LT
Quantity:
10 000
Company:
Part Number:
LTC4252A-2CMS#TRLTC4252A-2CMS
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS INFORMATION
current begins to decline below V
loop shuts off and GATE releases at time point 8. At time
point 9, the SENSE voltage falls below V
deactivates.
Large values of C
time out as V
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large C
may be exceeded during soft-start into a low impedance
load. A soft-start voltage below V
circuit breaker TIMER.
Power Limit Circuit Breaker
Figure 19 shows the LTC4252A-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board supply voltage, V
is set to be the same as the low supply operating voltage,
V
operating voltage, V
power at V
selected using the ratio:
SUPPLY(MIN)
SUPPLY(MIN)
ACL
= 43V. If the goal is to have the high supply
PWRGD
(t) may exceed the V
SENSE
TIMER
DRAIN
SS
GATE
SS
can cause premature circuit breaker
SUPPLY(MAX)
V
END OF INTIAL TIMING CYCLE
(18a) Without External C
12 34 567
GS(th)
, then resistors R4 and R6 are
SUPPLY
ACL
V
V
TMRH
TMRL
+ V
58μA
OS
Figure 18. Soft-Start Timing (All Waveforms Are Referenced to V
SS
)
. The D1 Zener voltage, V
OS
7a
values is SOA duration
ACL
= 71V giving the same
CB
CB
(t). The current limit
will not activate the
+ V
CB
DRN
OS
potential during
)
8 9
CB
58μA
SS
V
V
V
and TIMER
10
ACL
CB
DRNCL
5.8μA
V
DRNL
11
V
IN
– V
GATEH
Z
PWRGD
SENSE
TIMER
DRAIN
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
when
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
GATE
POWER
SS
V
V
POWER
R6
R4
SUPPLY
SUPPLY
END OF INTIAL TIMING CYCLE
V
R
12 3 4 5 6
GS(th)
LTC4252A-1/LTC4252A-2
=
(18b) With External C
S
V
V
V
TMRH
TMRL
SUPPLY(MAX)
FAULT
58μA
MAX
= 0.5 • (V
• V
LTC4252-1/LTC4252-2
⎝ ⎜
V
CB
=
OS
=1.064 •POWER
ACL
=
ACL
(
4 • V
•POWER
V
7
+ V
SUPPLY(MIN)
– V
SUPPLY(MIN)
DRN
OS
(
SUPPLY(MIN)
)
SUPPLY
8 9
EE
SS
58μA
)
SUPPLY(MIN)
V
V
V
10
ACL
CB
DRNCL
5.8μA
V
425212 F18
DRNL
CB
–V
11
V
+V
+ V
IN
+ V
SUPPLY(MIN)
• V
– V
OS
Z
SUPPLY(MAX)
)
)
SUPPLY(MAX)
GATEH
SUPPLY(MAX)
R6
R4
⎠ ⎟
)
) = 57V.
2
29
425212fc
(16)
(17)
(18)

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