LTC4252A-2CMS#TRPBF Linear Technology, LTC4252A-2CMS#TRPBF Datasheet - Page 24

• Manufacturer Part Number: LTC4252A-2CMS#TRPBF
• Description: IC CNTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-2CMS#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
Undervoltage Timing
In Figure 11 when UV pin drops below V
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
recovers and clears V
cycle begins followed by a GATE start-up cycle.
V
The V
similar timing behavior as the UV pin timing except it looks
for V
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When V
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 12, both UV and OV pins are connected together.
When UV clears V
24
IN
Undervoltage Lockout Timing
IN
IN
< (V
undervoltage lockout comparator, UVLO, has a
PWRGD
SENSE
TIMER
DRAIN
GATE
LKO
UV
SS
– V
UV DROPS BELOW V
1
UVHI
LKH
V
V
GATEL
UVLO
V
UVHI
UVHI
) to shut down and V
(time point 1), an initial timing
UV CLEARS V
2
(time point 2), an initial timer
Figure 11. Undervoltage Timing (All Waveforms Are Referenced to V
UVLO
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UVHI
IN
5.8μA
, CHECK OV CONDITION, GATE < V
INITIAL TIMING
UVLO
exits undervoltage
(time point 1),
IN
> V
V
ACL
TMRH
CB
LKO
OS
V
+ V
+ V
TMRL
OS
OS
to
)
)
3 4 56
58μA
TIMER CLEARS V
GATEL
cycle starts. If the system bus voltage overshoots V
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the V
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
Overvoltage Timing
During normal operation, if the OV pin exceeds V
shown at time point 1 of Figure 13, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull down
and the load is disconnected. At time point 2, OV recovers
and drops below the V
cycle begins. If the overvoltage glitch is long enough to
deplete the load capacitor, a full start-up cycle as shown
between time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 14a, the TIMER capacitor charges at 230μA if
the SENSE pin exceeds V
the SENSE pin drops below V
START-UP
, SENSE < V
GATE
7
58μA
8 9
DRN
10 11
TMRL
CB
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
– V
GATEH
5.8μA
OS
AND TIMER < V
GATEL
OVLO
CB
, SENSE < V
EE
)
threshold. A GATE start-up
but V
TMRL
CB
5.8μA
CB
before TIMER reaches
DRN
425212 F11
is less than 5V. If
OS
OVHI
425212fc
OVLO
OVHI
as