LTC4221IGN Linear Technology, LTC4221IGN Datasheet - Page 15

• Manufacturer Part Number: LTC4221IGN
• Description: IC CTRLR HOTSWAP DUAL 16SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4221IGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 1 V ~ 13.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
generate a logic high output to indicate that V
An internal high-to-low glitch filter helps to prevent nega-
tive voltage transients on each FB pin from deasserting its
PWRGD. The relationship between glitch filter time and an
FB pin transient voltage is shown in Figure 4. Using the
functionality of the PWRGD1 pin, the LTC4221 can be
configured to do sequential power-up and power-down as
shown by the circuit in Figure 5. Referring back to Figure 3,
ON2 is held low until V
exceed its undervoltage threshold at time point 5 when
PWRGD1 ramps up, pulling ON2 high. At time point 7, the
control logic sees ON2 exceeding its off threshold and so
commences a start-up cycle for channel 2. Similarly, when
ON1 is forced low by Q2 at time point 9, GATE1 is pulled
low by its 100μA pull-down while ON2 is held high by the
ON/OFF
70
60
80
50
40
30
20
10
V
V
0
Figure 4. FB Comparator Glitch Filter
Time vs Feedback Transient Voltage
CC1
CC2
0
20 40 60 80 100 120 140 160 180 200
CONNECTOR
BACKPLANE
FEEDBACK TRANSIENT (mV)
U
(FEMALE)
OUT1
U
Figure 5. Using PWRGD1 to Configure Sequential Power-Up/Power-Down
ramps high enough for FB1 to
CONNECTOR
PCB EDGE
(MALE)
W
LONG
LONG
SHORT
SHORT
LONG
T
Q2: 2N7002LT1
Z1: SMAJ10
* ADDITIONAL DETAILS
A
OMITTED FOR CLARITY
= 25°C
4221 F04
R5 10Ω
R3 10k
OUT
U
R6
10k
is valid.
Q2
R2
2k
R1
10k
10k
R4
R4 pull-up on PWRGD1. Its is only when channel 1 is
powered off and V
threshold at time point 10 that PWRGD1’s internal
N-channel MOSFET pull-down is triggered and ON2 goes
low. At time point 11, ON2 trips its off threshold and
GATE2 pulls low with a 100μA pull-down, powering off
channel 2.
For V
voltage comparator with a low-to-high threshold of 0.822V
and a low-to-high glitch filter of 18μs. This threshold is
designed to be 33% higher than the undervoltage thresh-
old. If either FB pin trips this threshold, the fault latch is set,
all GATE pins are pulled low with internal NFET pull-downs
and the LTC4221 goes into a fault state.
In the third function, each FB pin is used to control its
channel’s current limit during its start-up cycle. This will
be featured in the Start-Up Cycle with Current Limit
section.
GATE Pin Functions
Each GATE pin controls the gate of its channel’s external
N-channel MOSFET. Individual internal charge pumps
powered by V
and maximum 18V (internally clamped) for GATE1 and
GATE2. During UVLO, the internal charge pumps are off
and both GATE pins are pulled low by internal N-channel
MOSFET pull-downs. Outside UVLO, when ON1 is below
its off threshold, the charge pumps are on and GATE1 is
held low by an internal 100μA current pull-down. Once
16
10
1
6
OUT
ON1
ON2
PWRGD1
GND
Z1
LTC4221*
overvoltage detection, each FB pin has an over-
TIMER
SENSE1
9
GATE1
CC1
R
10Ω
C
1μF
V
X1
C
100nF
FB1
TIMER
CC1
X1
guarantee a gate drive of minimum 4.5V
OUT1
R
0.004Ω
SENSE1
discharges below its undervoltage
IRF7413
Q1
R
56k
R
15k
F1
F2
+
4221 F05
LTC4221
C
LOAD1
V
3.3V
5A
V
2.5V
5A
OUT1
OUT2
15
4221fa