LM5069MMX-1/NOPB National Semiconductor, LM5069MMX-1/NOPB Datasheet - Page 10

• Manufacturer Part Number: LM5069MMX-1/NOPB
• Description: IC CTLR HOT SWAP 48V 10-MSOP
• Manufacturer: National Semiconductor
• Type: Hot-Swap Controllerr

Specifications of LM5069MMX-1/NOPB

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 9 V ~ 80 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• For Use With: LM5069EVAL - BOARD EVALUATION LM5069
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM5069MMX-1

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limiting interval (t2 in Figure 3) an internal 85 µA fault timer
current source charges C
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 4.0V the 85 µA current source
is switched off, and C
current sink (t3 in Figure 3). The in-rush limiting interval is
complete when the voltage at the OUT pin increases to within
Gate Control
A charge pump provides internal bias voltage above the out-
put voltage (OUT pin) to enhance the N-Channel MOSFET’s
gate. The gate-to-source voltage is limited by an internal 12V
zener diode. During normal operating conditions (t3 in Figure
3) the gate of Q1 is held charged by an internal 16 µA current
source to approximately 12V above OUT. If the maximum
V
zener diode must be added between the GATE and OUT pins.
The external zener diode must have a forward current rating
of at least 250 mA.
When the system voltage is initially applied, the GATE pin is
held low by a 230 mA pull-down current. This helps prevent
an inadvertent turn-on of the MOSFET through its drain-gate
capacitance as the applied system voltage increases.
During the insertion time (t1 in Figure 3) the GATE pin is held
low by a 2 mA pull-down current. This maintains Q1 in the off-
GS
rating of Q1 is less than 12V, a lower voltage external
T
is discharged by the internal 2.5 µA
T
. If Q1’s power dissipation and the
FIGURE 3. Power Up Sequence (Current Limit only)
10
1.25V of the input voltage (V
high.
If the TIMER pin voltage reaches 4.0V before in-rush current
limiting or power limiting ceases (during t2), a fault is declared
and Q1 is turned off. See the Fault Timer & Restart section
for a complete description of the fault mode.
state until the end of t1, regardless of the voltage at VIN or
UVLO.
Following the insertion time, during t2 in Figure 3, the gate
voltage of Q1 is modulated to keep the current or power dis-
sipation level from exceeding the programmed levels. While
in the current or power limiting mode the TIMER pin capacitor
is charging. If the current and power limiting cease before the
TIMER pin reaches 4V the TIMER pin capacitor then dis-
charges, and the circuit enters normal operation.
If the in-rush limiting condition persists such that the TIMER
pin reached 4V during t2, the GATE pin is then pulled low by
the 2 mA pull-down current. The GATE pin is then held low
until either a power up sequence is initiated (LM5069-1), or
until the end of the restart sequence (LM5069-2). See the
Fault Timer & Restart section.
If the system input voltage falls below the UVLO threshold, or
rises above the OVLO threshold, the GATE pin is pulled low
by the 2 mA pull-down current to switch off Q1.
SYS
), and the PGD pin switches
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