MAX6974ATL+ Maxim Integrated Products, MAX6974ATL+ Datasheet - Page 16

• Manufacturer Part Number: MAX6974ATL+
• Description: IC LED DRIVER LINEAR 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Linear (Serial Interface)r

Specifications of MAX6974ATL+

• Topology: PWM
• Number Of Outputs: 24
• Internal Driver: Yes
• Type - Primary: General Purpose
• Type - Secondary: RGB
• Frequency: 33MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Voltage - Output: 7V
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 30mA
• Internal Switch(s): Yes
• Low Level Output Current: 6 mA
• High Level Output Current: 30 mA
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Supply Current: 77 mA
• Maximum Power Dissipation: 2963 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The serial interface uses the continuously running
clock, CLKI, to synchronously transfer and latch data
(33MHz max). The MAX6974/MAX6975 sample inputs
DIN and LOADI on the rising edge of CLKI and update
outputs DOUT and LOADO on the rising edge of CLKI.
The MAX6974/MAX6975 specifications guarantee that
cascaded devices observe setup and hold timing from
device to device, making external buffers and clock
trees unnecessary, even in very large systems.
The high-speed CLKI, CLKO, DIN, and DOUT signals
use low-voltage differential signaling (LVDS), and the
less frequently changing control signals, LOADI and
LOADO, use standard CMOS. The differential signals
are generally referred to in unipolar shorthand; for
example, the statement “CLKI rising edge” means that
CLKI+ is rising, and CLKI- is falling.
24-Output PWM LED Drivers
for Message Boards
Figure 6. Serial-Interface Timing
16
______________________________________________________________________________________
CLKI+
CLKI-
CLKO+
CLKO-
DIN+
DIN-
DOUT+
DOUT-
LOADI
LOADO
t
SU-LOADI
t
SU-DIN
t
t
PD-LOADO
t
PD-CLKO
PD-DOUT
t
HD-LOADI
t
HD-DIN
The MAX6974/MAX6975 use LVDS drivers with differential
signaling (300mV nominal logic swing around a +1.2V
bias) and cascaded CMOS control signals to minimize
signal-path EMI and simplify interface timing and print-
ed-circuit board (PCB) layout. Note the differential
inputs for the first driver can be driven from +3.3V
CMOS using LVDS level translators, such as the
MAX9112 terminated with 110Ω (see Figure 12).
A 25MHz to 33MHz clock frequency is recommended
to keep the display refresh rate high. When using the
MAX6975 in reduced global-intensity mode (GLB4 = 1
in configuration register), the recommended clock
frequency range is 6MHz to 33MHz.
The MAX6974/MAX6975 serial interface transfers all
data and control functions using a protocol structure
consisting of header, data, and optional tail segments
transmitted in this sequence. The header and tail
Serial-Interface Protocol Structure