ADP3419JRMZ-REEL ON Semiconductor, ADP3419JRMZ-REEL Datasheet - Page 3

• Manufacturer Part Number: ADP3419JRMZ-REEL
• Description: IC MOSFET DVR DUAL BOOTST 10MSOP
• Manufacturer: ON Semiconductor
• Type: High Side/Low Sider

Specifications of ADP3419JRMZ-REEL

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 32ns
• Current - Peak: 1A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 30V
• Voltage - Supply: 4.6 V ~ 6 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Number Of Drivers: 2
• Driver Configuration: Invert/Non-Invert
• Driver Type: High and Low Side
• Rise Time: 35ns
• Fall Time: 25ns
• Propagation Delay Time: 70ns
• Operating Supply Voltage (max): 6V
• Output Resistance: 1.7Ohm
• Operating Supply Voltage (min): 4.6V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 10
• Supply Voltage (min): 4.6 V
• Supply Current: 1.5 mA
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP3419JRMZ-REEL; ADP3419JRMZ-REELTR

1. For propagation delays, t
2. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of t
3. Guaranteed by characterization, not production tested.
PIN ASSIGNMENT
Pin No.
ELECTRICAL CHARACTERISTICS
temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)
HIGH-SIDE DRIVER
LOW-SIDE DRIVER
SUPPLY
Input Voltage High
Input Voltage Low
Input Current
DRVLSD Propagation Delay Time
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
Propagation Delay Times (Note 1)
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
Propagation Delay Times (Note 2)
SW Transition Timeout (Note 1 and 2)
Zero-Crossing Threshold
Supply Voltage Range
Supply Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
(Note 3)
10
1
2
3
4
5
6
7
8
9
Normal Mode
Shutdown Mode
Parameter
CROWBAR
Mnemonic
DRVLSD
DRVH
DRVL
VCC
GND
BST
SW
SD
IN
pdh
refers to the specified signal going high, and t
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling
this pin low turns on the low-side driver; pulling it high turns on the high-side driver.
Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled
and controlled by IN and by the adaptive overlap protection control circuitry.
Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition.
Input Supply. This pin should be bypassed to GND with a 4.7 mF or larger ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the
switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins
holds this bootstrapped voltage for the high-side MOSFET as it is switched.
t
t
V
pdl DRVLSD
pdh DRVLSD
CC
t
t
I
Symbol
t
t
I
pdhDRVH
pdhDRVL
pdlDRVH
SYS(NM)
pdlDRVL
SYS(SD)
t
t
t
t
t
rDRVH
fDRVH
rDRVL
fDRVL
SWTO
V
V
V
V
I
= SD = 5.0 V, BST = 4.0 V to 26 V. T
IN
ZC
CC
IH
IL
,
http://onsemi.com
Inputs = 0 V or 5.0 V
C
BST − SW = 4.6 V
BST − SW = 4.6 V
BST − SW = 4.6 V, C
BST − SW = 4.6 V, C
BST − SW = 4.6 V, C
BST − SW = 4.6 V, C
C
C
C
C
BST − SW = 4.6 V
I
I
V
V
CC
CC
CC
CC
LOAD
LOAD
LOAD
LOAD
LOAD
+ I
+ I
rising
falling
BST
BST
= 3 nF, Figure 3
= 3 nF, Figure 4
= 3 nF, Figure 4
= 3 nF, Figure 4
= 3 nF, Figure 4
3
, IN = 0 V or 5.0 V
, SD = 0 V
Conditions
pdl
refers to the signal going low with transitions measured at 50%.
Description
LOAD
LOAD
LOAD
LOAD
A
= 3 nF, Figure 4
= 3 nF, Figure 4
= 3 nF, Figure 4
= 3 nF, Figure 4
= 0°C to 100°C, unless otherwise noted All limits at
−1.0
Min
150
2.0
4.6
3.8
15
50
SWTO
4.25
Typ
350
325
120
1.7
0.8
1.7
0.8
1.0
0.8
20
14
32
28
13
25
16
11
11
.
Max
+1.0
600
600
0.8
3.3
2.3
3.3
2.3
6.0
1.5
4.5
35
25
70
60
30
25
48
30
Unit
mA
mV
mA
mA
ns
ns
ns
ns
ns
ns
W
W
W
W
V
V
V
V
V