TC4423COE713 Microchip Technology, TC4423COE713 Datasheet - Page 9
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TC4423COE713
Manufacturer Part Number
TC4423COE713
Description
IC MOSFET DVR 3A DUAL HS 16-SOIC
Manufacturer
Microchip Technology
Type
Microcontrollerr
Datasheet
1.TC4424CPA.pdf
(18 pages)
Specifications of TC4423COE713
Configuration
Low-Side
Input Type
Inverting
Delay Time
33ns
Current - Peak
3A
Number Of Configurations
2
Number Of Outputs
2
Voltage - Supply
4.5 V ~ 18 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Rise Time
35 ns
Fall Time
35 ns
Supply Voltage (min)
4.5 V
Supply Current
2.5 mA
Maximum Power Dissipation
470 mW
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Number Of Drivers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.0
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
Inputs A and B are TTL/CMOS compatible inputs that
control outputs A and B, respectively. These inputs
have 300 mV of hysteresis between the high and low
input levels, allowing them to be driven from slow rising
and falling signals, and to provide noise immunity.
3.2
Outputs A and B are CMOS push-pull outputs that are
capable of sourcing and sinking 3A peaks of current
(V
gate of the external MOSFET will stay in the intended
state even during large transients. These outputs also
have a reverse current latch-up rating of 1.5A.
3.3
V
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local ceramic capacitor.
This bypass capacitor provides a localized low-
impedance path for the peak currents that are to be
provided to the load.
2004 Microchip Technology Inc.
Note 1:
8-Pin PDIP
DD
DD
is the bias supply input for the MOSFET driver and
= 18V). The low output impedance ensures the
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1
2
3
4
5
6
7
8
PIN DESCRIPTIONS
Inputs A and B
Outputs A and B
Supply Input (V
Duplicate pins must be connected for proper operation.
8-Pin
DFN
PAD
PIN FUNCTION TABLE
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1
2
3
4
5
6
7
8
16-Pin
(Wide)
SOIC
DD
10
12
13
14
15
16
11
—
1
2
3
4
5
6
7
8
9
)
Symbol
OUT B
OUT B
OUT A
OUT A
GND
GND
IN A
IN B
V
V
NC
NC
NC
NC
NC
NC
NC
DD
DD
(1)
No connection
Input A
No connection
Ground
Ground
No connection
Input B
No connection
No connection
Output B
Output B
Supply input
Supply input
Output A
Output A
No connection
Exposed Metal Pad
TC4423/TC4424/TC4425
3.4
Ground is the device return pin. The ground pin(s)
should have a low-impedance connection to the bias
supply source return. High peak currents will flow out
the ground pin(s) when the capacitive load is being
discharged.
3.5
The exposed metal pad of the 6x5 DFN package is not
internally connected to any potential. Therefore, this
pad can be connected to a ground plane or other cop-
per plane on a printed circuit board to aid in heat
removal from the package.
Ground (GND)
Exposed Metal Pad
Description
DS21421D-page 9