ATA6823-PHQW Atmel, ATA6823-PHQW Datasheet - Page 16

• Manufacturer Part Number: ATA6823-PHQW
• Description: IC H-BRIDGE MOTOR DRIVER 32-QFN
• Manufacturer: Atmel
• Type: H-Bridge Motor Driverr

Specifications of ATA6823-PHQW

• Configuration: H Bridge
• Input Type: PWM
• Delay Time: 4.25µs
• Current - Peak: 350mA
• Number Of Configurations: 1
• Number Of Outputs: 4
• Voltage - Supply: 6.5 V ~ 21.2 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Supply Voltage: 7 V to 18 V
• Supply Current: 7 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these
limits is not implied unless otherwise stated explicitly.
7. Noise and Surge Immunity, ESD and Latch-up
16
Parameters
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
Normal functionality
Normal functionality, overtemperature warning
Drivers for H1, H2, L1, L2, and LIN are switched
OFF, VCC regulator is OFF
Note:
Parameters
Conducted interferences
Conducted disturbances
ESD according to IBEE LIN EMC
- Pins LIN, PBAT, VBAT
- Pin EN2 (33k serial resistor)
ESD HBM with 1.5k /100pF
ESD HBM with 1.5k /100pF
Pins EN2, LIN, PBAT, VBAT against GND
ESD CDM (field induced method)
Note:
1. Full functionality
2. H-bridge drivers are switched off (undervoltage detection)
3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly
4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct
5. H-bridge drivers are switched off
6. Full LIN functionality in conformance with LIN specification 2.1
1. Test pulse 5: V
Atmel ATA6823
(1)
(2)
(3)
(4)
(5)
(6)
bat max
Static latch-up tested according to AEC-Q100-004 and JESD78.
In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V
when not able to drive the specified current.
• 3 to 6 samples, 0 failures
• Electrical post stress testing at room temperature
= 40V
Standard and Test Conditions
ISO 7637-1
CISP25
Test specification 1.0 following IEC 61000-4-2
ESD- STM5.1-2001
JESD22-A114E 2007
CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref_D
ESD- STM5.1-2001
JESD22-A114E 2007
CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref_D
ESD STM5.3.1 - 1999
Symbol
V
V
V
V
V
V
VBAT1
VBAT2
VBAT3
VBAT4
VBAT5
VBAT6
T
T
T
j
j
j
> V
V
Min.
–40
150
165
THUV
6
3
0
7
THOV
V
V
±6kV
±5kV
±4kV
±8kV
±1kV
Max.
+150
165
180
< 6
< 3
THOV
THUV
40
18
Level 4
Level 5
Value
4856K–AUTO–01/11
(1)
Unit
°C
°C
°C
V
V
V
V
V
V