LM5109BMA/NOPB National Semiconductor, LM5109BMA/NOPB Datasheet - Page 7

• Manufacturer Part Number: LM5109BMA/NOPB
• Description: IC DVR HALF-BRIDGE 90V 1A 8-SOIC
• Manufacturer: National Semiconductor

Specifications of LM5109BMA/NOPB

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 32ns
• Current - Peak: 1A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 108V
• Voltage - Supply: 8 V ~ 14 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM5109BMA; *LM5109BMA/NOPB; LM5109BMA

Timing Diagram
Layout Considerations
Optimum performance of high and low-side gate drivers can-
not be achieved without taking due considerations during
circuit board layout. The following points are emphasized:
1.
2.
3.
4.
Low ESR / ESL capacitors must be connected close to
the IC between VDD and VSS pins and between HB and
HS pins to support high peak currents being drawn from
VDD and HB during the turn-on of the external
MOSFETs.
To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor and a good
quality ceramic capacitor must be connected between
the MOSFET drain and ground (VSS).
In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances between the
source of the top MOSFET and the drain of the bottom
MOSFET (synchronous rectifier) must be minimized.
Grounding considerations:
a) The first priority in designing grounding connections is
to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area.
This will decrease the loop inductance and minimize
noise issues on the gate terminals of the MOSFETs. The
gate driver should be placed as close as possible to the
MOSFETs.
b) The second consideration is the high current path that
includes the bootstrap capacitor, the bootstrap diode, the
local ground referenced bypass capacitor, and the low-
side MOSFET body diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the
bootstrap diode from the ground referenced VDD bypass
capacitor. The recharging occurs in a short time interval
FIGURE 3.
7
HS Transient Voltages Below
Ground
The HS node will always be clamped by the body diode of the
lower external FET. In some situations, board resistances and
inductances can cause the HS node to transiently swing sev-
eral volts below ground. The HS node can swing below
ground provided:
1.
2.
3.
and involves high peak current. Minimizing this loop
length and area on the circuit board is important to ensure
reliable operation.
HS must always be at a lower potential than HO. Pulling
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current flow from the
HB supply, possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
HB to HS operating voltage should be 15V or less.
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
Low ESR bypass capacitors from HB to HS and from
VDD to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with
the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable
operation.
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