MCZ33937AEK Freescale Semiconductor, MCZ33937AEK Datasheet - Page 29

• Manufacturer Part Number: MCZ33937AEK
• Description: IC PRE-DRIVER 3PH ENH 54-SOIC
• Manufacturer: Freescale Semiconductor
• Series: SMARTMOS™r
• Type: 3 Phase Pre-Driverr

Specifications of MCZ33937AEK

• Configuration: 3 Phase Bridge
• Input Type: Non-Inverting
• Delay Time: 265ns
• Current - Peak: 600mA
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 15V
• Voltage - Supply: 8 V ~ 40 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Side external FETs, a fully integrated trickle charge pump
provides the charge necessary to maintain the external FET
gates at fully enhanced levels. The trickle charge pump has
limited ability to supply external leakage paths while
performing it’s primary function. The graphs in
through
supplying external current loads. These limits are based on
maintaining the voltage at CBOOT at least 3.0 V greater than
the voltage on the HS_S for that phase. If this voltage
differential becomes less than 3.0 V, the corresponding high
side FET will most likely not remain fully enhanced and the
high side driver may malfunction due to insufficient bias
voltage between CBOOT and HS_S.
driver output impedance, overall (external and internal) gate
resistance and the load capacitance. To ensure the Low Side
FET is not turned on by a large positive dV/dt on the drain of
the Low Side FET, the turn-on slew rate of the High Side
should be limited. If the slew rate of the High Side is limited
by the gate-drain capacitance of the High Side FET, then the
displacement current injected into the Low Side gate drive
output will be approximately the same value. Therefore, to
ensure the Low Side drivers can be held off, the voltage drop
across the Low Side gate driver must be lower than the
threshold voltage of the Low Side FET (see
will be able to remain off if its gate drive Low Side switch,
develops a voltage drop less than the threshold voltage of the
High Side FET. The gate drive Low Side switch discharges
the gate to the source.
could be forced below ground. The Low Side FETs must not
inject detrimental substrate currents in this condition.
the load current during switching.
Analog Integrated Circuit Device Data
Freescale Semiconductor
In order to achieve a 100% duty cycle operation of the High
The slew rate of the external output FET is limited by the
Similarly, during large negative dV/dt, the High Side FET
Additionally, during negative dV/dt the Low Side gate drive
The occurrence of these cases depends on the polarity of
14
beginning on page
21
show the typical margin for
Figure
Figures 11
17).
DRIVER FAULT PROTECTION
against various faults. The first of them is the Current Sense
Amplifier with the Over-current Comparator. These two
blocks are common for all three driver phases.
Current Sense Amplifier
amplifier (see
the external FETs as a voltage across the current sense
resistor R
does not extend below ground, it is necessary to use an
external reference to permit measuring both positive and
negative currents.
microcontroller’s ADC) at the AMP_OUT pin, providing the
means for closed loop control with the 33937.
current Comparator threshold voltage (see
Over-current Comparator
pre-set threshold value by the over-current comparator input.
If the Current Sense Amplifier output voltage exceeds the
threshold of the Over-current Comparator it would change
the status of its output (OC_OUT pin) and the fault condition
would be latched (see
return value of the Status Register 0. If the proper Interrupt
Mask has been set, this fault condition will generate an
The 33937 IC integrates several protection mechanisms
This amplifier is usually connected as a differential
The amplifier output can be monitored directly (e.g. by the
The output voltage is internally compared with the Over-
The amplified voltage across R
The occurrence of this fault would be signalled by the
V SUP
LS
Control
VLS
Px_HS_G
Px_LS_G
SENSE
33927
Figure 17. Positive DV/dt Transient
Z o
Figure
Driver
-V D
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
-Side
Low
. Since the amplifier common mode range
Px_LS_S
Deadtime
Px_LS_G
Px_HS_S
9). It senses a current flowing through
i CDG
Figure
G
20).
-
R g
dV/dt
SENSE
Phase x Output Voltage
+
C DG
C GS
is compared with the
Phase
Return
D
S
Figure
Phase x
Output
C DS
22).
Discrete
FET
Package
33937
29