LTC1710CMS8#TR Linear Technology, LTC1710CMS8#TR Datasheet - Page 5

• Manufacturer Part Number: LTC1710CMS8#TR
• Description: IC SWITCH SMBUS DUAL HISD 8MSOP
• Manufacturer: Linear Technology
• Type: High Sider

Specifications of LTC1710CMS8#TR

• Input Type: 2-Wire SMBus
• Number Of Outputs: 2
• On-state Resistance: 400 mOhm
• Current - Output / Channel: 300mA
• Current - Peak Output: 1A
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Switch Type: High Side
• Power Switch Family: LTC1710
• Input Voltage: 2.7 to 5.5V
• Power Switch On Resistance: 550mOhm
• Mounting: Surface Mount
• Supply Current: 17uA
• Package Type: MSOP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Pin Count: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

BLOCK DIAGRA
OPERATIO
SMBus Operation
SMBus is a serial bus interface that uses only two bus lines,
DATA and CLK, to control low power peripheral devices in
portable equipment. It consists of masters, also known as
hosts, and slave devices. The master of the SMBus is
always the one to initiate communications to the slave
devices by varying the status of the DATA and CLK lines.
The SMBus specification establishes a set of protocols that
devices on the bus must follow for communications.
TI I G DIAGRA
W
DATA
AD1
V
CLK
U
CC
DATA
8
6
5
3
CLK
t
SU:STA
BUFFERS
INPUT
U
START
DETECTORS
REGISTER
COUNTER
ADDRESS
DECODER
W
START
STOP
SHIFT
W
AND
t
HD:STA
COMPARATOR
t
ADDRESS
SU:DAT
V
t
CC
HIGH
LOGIC
t
HD:DAT
t
r
A
B
ACK
The protocol that the LTC1710 uses is the Send Byte Pro-
tocol. In this protocol, the master first sends out a Start
signal by switching the DATA line from high to low while
CLK is high. (Because there may be more than one master
on the same bus, an arbitration process takes place if two
masters attempt to take control of the DATA line simulta-
neously; the first master that outputs a one while the other
master is zero loses the arbitration and becomes a slave
itself.) Upon detecting this Start signal, all slave devices on
the bus wake up and prepare to shift in the next byte of data.
UNDERVOLTAGE
LATCHES
2V
t
OUTPUT
f
LOCKOUT
t
LOW
REGULATED
CHARGE
PUMPS
POWER-ON
RESET
SHUTDOWN
THERMAL
STOP
t
SU:STO
V
CC
LTC1710
1710 TD
7
1
2
4
1710 BD
OUT1
SW0D
OUT0
GND
5